1 /* 2 * pcm051.h 3 * 4 * Phytec phyCORE-AM335x (pcm051) boards information header 5 * 6 * Copyright (C) 2013 Lemonage Software GmbH 7 * Author Lars Poeschel <poeschel@lemonage.de> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 14 * kind, whether express or implied; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __CONFIG_PCM051_H 20 #define __CONFIG_PCM051_H 21 22 #define CONFIG_AM33XX 23 #define CONFIG_OMAP 24 #define CONFIG_OMAP_COMMON 25 26 #include <asm/arch/omap.h> 27 28 #define CONFIG_DMA_COHERENT 29 #define CONFIG_DMA_COHERENT_SIZE (1 << 20) 30 31 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 32 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 33 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 34 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 35 #define CONFIG_SYS_PROMPT "U-Boot# " 36 #define CONFIG_SYS_NO_FLASH 37 #define MACH_TYPE_PCM051 4144 /* Until the next sync */ 38 #define CONFIG_MACH_TYPE MACH_TYPE_PCM051 39 40 #define CONFIG_OF_LIBFDT 41 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 42 #define CONFIG_SETUP_MEMORY_TAGS 43 #define CONFIG_INITRD_TAG 44 45 /* commands to include */ 46 #include <config_cmd_default.h> 47 48 #define CONFIG_CMD_ASKENV 49 #define CONFIG_VERSION_VARIABLE 50 51 /* set to negative value for no autoboot */ 52 #define CONFIG_BOOTDELAY 1 53 #define CONFIG_ENV_VARS_UBOOT_CONFIG 54 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 55 #define CONFIG_EXTRA_ENV_SETTINGS \ 56 "loadaddr=0x80007fc0\0" \ 57 "fdtaddr=0x80000000\0" \ 58 "rdaddr=0x81000000\0" \ 59 "bootfile=uImage\0" \ 60 "fdtfile=pcm051.dtb\0" \ 61 "console=ttyO0,115200n8\0" \ 62 "optargs=\0" \ 63 "mmcdev=0\0" \ 64 "mmcroot=/dev/mmcblk0p2 ro\0" \ 65 "mmcrootfstype=ext4 rootwait\0" \ 66 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ 67 "ramrootfstype=ext2\0" \ 68 "mmcargs=setenv bootargs console=${console} " \ 69 "${optargs} " \ 70 "root=${mmcroot} " \ 71 "rootfstype=${mmcrootfstype}\0" \ 72 "bootenv=uEnv.txt\0" \ 73 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ 74 "importbootenv=echo Importing environment from mmc ...; " \ 75 "env import -t $loadaddr $filesize\0" \ 76 "ramargs=setenv bootargs console=${console} " \ 77 "${optargs} " \ 78 "root=${ramroot} " \ 79 "rootfstype=${ramrootfstype}\0" \ 80 "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ 81 "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ 82 "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ 83 "mmcboot=echo Booting from mmc ...; " \ 84 "run mmcargs; " \ 85 "bootm ${loadaddr}\0" \ 86 "ramboot=echo Booting from ramdisk ...; " \ 87 "run ramargs; " \ 88 "bootm ${loadaddr}\0" \ 89 90 #define CONFIG_BOOTCOMMAND \ 91 "mmc dev ${mmcdev}; if mmc rescan; then " \ 92 "echo SD/MMC found on device ${mmcdev};" \ 93 "if run loadbootenv; then " \ 94 "echo Loaded environment from ${bootenv};" \ 95 "run importbootenv;" \ 96 "fi;" \ 97 "if test -n $uenvcmd; then " \ 98 "echo Running uenvcmd ...;" \ 99 "run uenvcmd;" \ 100 "fi;" \ 101 "if run loaduimage; then " \ 102 "run mmcboot;" \ 103 "fi;" \ 104 "fi;" \ 105 106 /* Clock Defines */ 107 #define V_OSCK 25000000 /* Clock output from T2 */ 108 #define V_SCLK (V_OSCK) 109 110 #define CONFIG_CMD_ECHO 111 112 /* max number of command args */ 113 #define CONFIG_SYS_MAXARGS 16 114 115 /* Console I/O Buffer Size */ 116 #define CONFIG_SYS_CBSIZE 512 117 118 /* Print Buffer Size */ 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 120 + sizeof(CONFIG_SYS_PROMPT) + 16) 121 122 /* Boot Argument Buffer Size */ 123 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 124 125 /* 126 * memtest works on 8 MB in DRAM after skipping 32MB from 127 * start addr of ram disk 128 */ 129 #define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) 130 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ 131 + (8 * 1024 * 1024)) 132 133 #define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */ 134 135 #define CONFIG_MMC 136 #define CONFIG_GENERIC_MMC 137 #define CONFIG_OMAP_HSMMC 138 #define CONFIG_CMD_MMC 139 #define CONFIG_DOS_PARTITION 140 #define CONFIG_CMD_FAT 141 #define CONFIG_CMD_EXT2 142 143 #define CONFIG_SPI 144 #define CONFIG_OMAP3_SPI 145 #define CONFIG_MTD_DEVICE 146 #define CONFIG_SPI_FLASH 147 #define CONFIG_SPI_FLASH_WINBOND 148 #define CONFIG_CMD_SF 149 #define CONFIG_SF_DEFAULT_SPEED 24000000 150 151 /* Physical Memory Map */ 152 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ 153 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ 154 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */ 155 156 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 157 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 158 GENERATED_GBL_DATA_SIZE) 159 /* Platform/Board specific defs */ 160 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 161 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 162 #define CONFIG_SYS_HZ 1000 /* 1ms clock */ 163 164 #define CONFIG_CONS_INDEX 1 165 /* NS16550 Configuration */ 166 #define CONFIG_SYS_NS16550 167 #define CONFIG_SYS_NS16550_SERIAL 168 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 169 #define CONFIG_SYS_NS16550_CLK (48000000) 170 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ 171 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ 172 #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ 173 #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ 174 #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ 175 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ 176 177 /* I2C Configuration */ 178 #define CONFIG_I2C 179 #define CONFIG_CMD_I2C 180 #define CONFIG_HARD_I2C 181 #define CONFIG_SYS_I2C_SPEED 100000 182 #define CONFIG_SYS_I2C_SLAVE 1 183 #define CONFIG_I2C_MULTI_BUS 184 #define CONFIG_DRIVER_OMAP24XX_I2C 185 #define CONFIG_CMD_EEPROM 186 #define CONFIG_ENV_EEPROM_IS_ON_I2C 187 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 189 #define CONFIG_SYS_I2C_MULTI_EEPROMS 190 191 #define CONFIG_OMAP_GPIO 192 193 #define CONFIG_BAUDRATE 115200 194 #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 195 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } 196 197 /* CPU */ 198 #define CONFIG_ARCH_CPU_INIT 199 200 #define CONFIG_ENV_OVERWRITE 201 #define CONFIG_SYS_CONSOLE_INFO_QUIET 202 203 #define CONFIG_ENV_IS_NOWHERE 204 205 /* Defines for SPL */ 206 #define CONFIG_SPL 207 #define CONFIG_SPL_FRAMEWORK 208 /* 209 * Place the image at the start of the ROM defined image space. 210 * We limit our size to the ROM-defined downloaded image area, and use the 211 * rest of the space for stack. 212 */ 213 #define CONFIG_SPL_TEXT_BASE 0x402F0400 214 #define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) 215 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 216 217 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 218 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 219 220 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 221 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 222 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 223 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 224 #define CONFIG_SPL_MMC_SUPPORT 225 #define CONFIG_SPL_FAT_SUPPORT 226 #define CONFIG_SPL_I2C_SUPPORT 227 228 #define CONFIG_SPL_LIBCOMMON_SUPPORT 229 #define CONFIG_SPL_LIBDISK_SUPPORT 230 #define CONFIG_SPL_LIBGENERIC_SUPPORT 231 #define CONFIG_SPL_SERIAL_SUPPORT 232 #define CONFIG_SPL_GPIO_SUPPORT 233 #define CONFIG_SPL_YMODEM_SUPPORT 234 #define CONFIG_SPL_NET_SUPPORT 235 #define CONFIG_SPL_ENV_SUPPORT 236 #define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL" 237 #define CONFIG_SPL_ETH_SUPPORT 238 #define CONFIG_SPL_SPI_SUPPORT 239 #define CONFIG_SPL_SPI_FLASH_SUPPORT 240 #define CONFIG_SPL_SPI_LOAD 241 #define CONFIG_SPL_SPI_BUS 0 242 #define CONFIG_SPL_SPI_CS 0 243 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 244 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 245 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" 246 247 /* 248 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 249 * 64 bytes before this address should be set aside for u-boot.img's 250 * header. That is 0x800FFFC0--0x80100000 should not be used for any 251 * other needs. 252 */ 253 #define CONFIG_SYS_TEXT_BASE 0x80800000 254 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 255 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 256 257 /* Since SPL did pll and ddr initialization for us, 258 * we don't need to do it twice. 259 */ 260 #ifndef CONFIG_SPL_BUILD 261 #define CONFIG_SKIP_LOWLEVEL_INIT 262 #endif 263 264 /* 265 * USB configuration 266 */ 267 #define CONFIG_USB_MUSB_DSPS 268 #define CONFIG_ARCH_MISC_INIT 269 #define CONFIG_MUSB_GADGET 270 #define CONFIG_MUSB_PIO_ONLY 271 #define CONFIG_USB_GADGET_DUALSPEED 272 #define CONFIG_MUSB_HOST 273 #define CONFIG_AM335X_USB0 274 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL 275 #define CONFIG_AM335X_USB1 276 #define CONFIG_AM335X_USB1_MODE MUSB_HOST 277 278 #ifdef CONFIG_MUSB_HOST 279 #define CONFIG_CMD_USB 280 #define CONFIG_USB_STORAGE 281 #endif 282 283 #ifdef CONFIG_MUSB_GADGET 284 #define CONFIG_USB_ETHER 285 #define CONFIG_USB_ETH_RNDIS 286 #endif /* CONFIG_MUSB_GADGET */ 287 288 /* Unsupported features */ 289 #undef CONFIG_USE_IRQ 290 291 #define CONFIG_CMD_NET 292 #define CONFIG_CMD_DHCP 293 #define CONFIG_CMD_PING 294 #define CONFIG_DRIVER_TI_CPSW 295 #define CONFIG_MII 296 #define CONFIG_BOOTP_DEFAULT 297 #define CONFIG_BOOTP_DNS 298 #define CONFIG_BOOTP_DNS2 299 #define CONFIG_BOOTP_SEND_HOSTNAME 300 #define CONFIG_BOOTP_GATEWAY 301 #define CONFIG_BOOTP_SUBNETMASK 302 #define CONFIG_NET_RETRY_COUNT 10 303 #define CONFIG_NET_MULTI 304 #define CONFIG_PHY_GIGE 305 #define CONFIG_PHYLIB 306 #define CONFIG_PHY_ADDR 0 307 #define CONFIG_PHY_SMSC 308 309 #endif /* ! __CONFIG_PCM051_H */ 310