1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_PB1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #ifdef CONFIG_PB1000 21 #define CONFIG_SOC_AU1000 1 22 #else 23 #ifdef CONFIG_PB1100 24 #define CONFIG_SOC_AU1100 1 25 #else 26 #ifdef CONFIG_PB1500 27 #define CONFIG_SOC_AU1500 1 28 #else 29 #error "No valid board set" 30 #endif 31 #endif 32 #endif 33 34 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 35 36 #define CONFIG_BAUDRATE 115200 37 38 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 39 #undef CONFIG_BOOTARGS 40 41 #define CONFIG_EXTRA_ENV_SETTINGS \ 42 "addmisc=setenv bootargs ${bootargs} " \ 43 "console=ttyS0,${baudrate} " \ 44 "panic=1\0" \ 45 "bootfile=/vmlinux.img\0" \ 46 "load=tftp 80500000 ${u-boot}\0" \ 47 "" 48 /* Boot from NFS root */ 49 #define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" 50 51 /* 52 * Miscellaneous configurable options 53 */ 54 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 55 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 56 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 57 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 58 59 #define CONFIG_SYS_MALLOC_LEN 128*1024 60 61 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 62 63 #define CONFIG_SYS_MIPS_TIMER_FREQ 396000000 64 65 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 66 67 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 68 69 #define CONFIG_SYS_MEMTEST_START 0x80100000 70 #undef CONFIG_SYS_MEMTEST_START 71 #define CONFIG_SYS_MEMTEST_START 0x80200000 72 #define CONFIG_SYS_MEMTEST_END 0x83800000 73 74 /*----------------------------------------------------------------------- 75 * FLASH and environment organization 76 */ 77 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 78 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 79 80 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 81 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 82 83 /* The following #defines are needed to get flash environment right */ 84 /* ROM version */ 85 /* #define CONFIG_SYS_TEXT_BASE 0xbfc00000 */ 86 /* SDRAM version */ 87 #define CONFIG_SYS_TEXT_BASE 0x83800000 88 89 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 90 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 91 92 #define CONFIG_SYS_INIT_SP_OFFSET 0x4000000 93 94 /* We boot from this flash, selected with dip switch */ 95 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 96 97 /* timeout values are in ticks */ 98 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 99 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 100 101 #define CONFIG_ENV_IS_NOWHERE 1 102 103 /* Address and size of Primary Environment Sector */ 104 #define CONFIG_ENV_ADDR 0xB0030000 105 #define CONFIG_ENV_SIZE 0x10000 106 107 #define CONFIG_FLASH_16BIT 108 109 #define CONFIG_NR_DRAM_BANKS 2 110 111 112 #define CONFIG_MEMSIZE_IN_BYTES 113 114 115 /*---USB -------------------------------------------*/ 116 #if 0 117 #define CONFIG_USB_OHCI 118 #define CONFIG_USB_STORAGE 119 #define CONFIG_DOS_PARTITION 120 #endif 121 122 /*---ATA PCMCIA ------------------------------------*/ 123 #if 0 124 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 125 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 126 #define CONFIG_PCMCIA_SLOT_A 127 128 #define CONFIG_ATAPI 1 129 #define CONFIG_MAC_PARTITION 1 130 131 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 132 #define CONFIG_IDE_PCMCIA 1 133 134 /* We only support one slot for now */ 135 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 136 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 137 138 #undef CONFIG_IDE_LED /* LED for ide not supported */ 139 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 140 141 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 142 143 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 144 145 /* Offset for data I/O */ 146 #define CONFIG_SYS_ATA_DATA_OFFSET 8 147 148 /* Offset for normal register accesses */ 149 #define CONFIG_SYS_ATA_REG_OFFSET 0 150 151 /* Offset for alternate registers */ 152 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 153 154 #endif 155 /*----------------------------------------------------------------------- 156 * Cache Configuration 157 */ 158 #define CONFIG_SYS_DCACHE_SIZE 16384 159 #define CONFIG_SYS_ICACHE_SIZE 16384 160 #define CONFIG_SYS_CACHELINE_SIZE 32 161 162 163 /* 164 * BOOTP options 165 */ 166 #define CONFIG_BOOTP_BOOTFILESIZE 167 #define CONFIG_BOOTP_BOOTPATH 168 #define CONFIG_BOOTP_GATEWAY 169 #define CONFIG_BOOTP_HOSTNAME 170 171 172 /* 173 * Command line configuration. 174 */ 175 #define CONFIG_CMD_DHCP 176 #define CONFIG_CMD_MII 177 #define CONFIG_CMD_PING 178 179 #undef CONFIG_CMD_FAT 180 #undef CONFIG_CMD_IDE 181 #undef CONFIG_CMD_BEDBUG 182 183 #endif /* __CONFIG_H */ 184