110a03382SStephen Warren /* 210a03382SStephen Warren * Copyright (c) 2013-2016, NVIDIA CORPORATION. 310a03382SStephen Warren * 410a03382SStephen Warren * SPDX-License-Identifier: GPL-2.0 510a03382SStephen Warren */ 610a03382SStephen Warren 710a03382SStephen Warren #ifndef _P2771_0000_H 810a03382SStephen Warren #define _P2771_0000_H 910a03382SStephen Warren 1010a03382SStephen Warren #include <linux/sizes.h> 1110a03382SStephen Warren 1210a03382SStephen Warren #include "tegra186-common.h" 1310a03382SStephen Warren 1410a03382SStephen Warren /* High-level configuration options */ 1510a03382SStephen Warren #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" 1610a03382SStephen Warren 17ad3c144fSBryan Wu /* I2C */ 18ad3c144fSBryan Wu #define CONFIG_SYS_I2C_TEGRA 19ad3c144fSBryan Wu 2010a03382SStephen Warren /* Environment in eMMC, at the end of 2nd "boot sector" */ 2110a03382SStephen Warren #define CONFIG_SYS_MMC_ENV_DEV 0 2210a03382SStephen Warren #define CONFIG_SYS_MMC_ENV_PART 2 2310a03382SStephen Warren #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 2410a03382SStephen Warren 25*a6bb0084SStephen Warren /* PCI host support */ 26*a6bb0084SStephen Warren 2710a03382SStephen Warren #include "tegra-common-post.h" 2810a03382SStephen Warren 2910a03382SStephen Warren /* Crystal is 38.4MHz. clk_m runs at half that rate */ 3010a03382SStephen Warren #define COUNTER_FREQUENCY 19200000 3110a03382SStephen Warren 3210a03382SStephen Warren #endif 33