1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MMC_MINIMAL 185 #define CONFIG_SPL_FLUSH_IMAGE 186 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 187 #define CONFIG_FSL_LAW /* Use common FSL init code */ 188 #define CONFIG_SYS_TEXT_BASE 0x11001000 189 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 190 #define CONFIG_SPL_PAD_TO 0x20000 191 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 192 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 193 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 194 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 195 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 196 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 197 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 198 #define CONFIG_SPL_MMC_BOOT 199 #ifdef CONFIG_SPL_BUILD 200 #define CONFIG_SPL_COMMON_INIT_DDR 201 #endif 202 #endif 203 204 #ifdef CONFIG_SPIFLASH 205 #define CONFIG_SPL_SPI_SUPPORT 206 #define CONFIG_SPL_SPI_FLASH_MINIMAL 207 #define CONFIG_SPL_FLUSH_IMAGE 208 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 209 #define CONFIG_FSL_LAW /* Use common FSL init code */ 210 #define CONFIG_SYS_TEXT_BASE 0x11001000 211 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 212 #define CONFIG_SPL_PAD_TO 0x20000 213 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 214 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 215 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 216 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 217 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 218 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 219 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 220 #define CONFIG_SPL_SPI_BOOT 221 #ifdef CONFIG_SPL_BUILD 222 #define CONFIG_SPL_COMMON_INIT_DDR 223 #endif 224 #endif 225 226 #ifdef CONFIG_NAND 227 #ifdef CONFIG_TPL_BUILD 228 #define CONFIG_SPL_NAND_BOOT 229 #define CONFIG_SPL_FLUSH_IMAGE 230 #define CONFIG_SPL_NAND_INIT 231 #define CONFIG_SPL_COMMON_INIT_DDR 232 #define CONFIG_SPL_MAX_SIZE (128 << 10) 233 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 234 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 235 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 236 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 237 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 238 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 239 #elif defined(CONFIG_SPL_BUILD) 240 #define CONFIG_SPL_INIT_MINIMAL 241 #define CONFIG_SPL_FLUSH_IMAGE 242 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 243 #define CONFIG_SPL_TEXT_BASE 0xff800000 244 #define CONFIG_SPL_MAX_SIZE 4096 245 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 246 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 247 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 248 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 249 #endif /* not CONFIG_TPL_BUILD */ 250 251 #define CONFIG_SPL_PAD_TO 0x20000 252 #define CONFIG_TPL_PAD_TO 0x20000 253 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 254 #define CONFIG_SYS_TEXT_BASE 0x11001000 255 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 256 #endif 257 258 #ifndef CONFIG_SYS_TEXT_BASE 259 #define CONFIG_SYS_TEXT_BASE 0xeff40000 260 #endif 261 262 #ifndef CONFIG_RESET_VECTOR_ADDRESS 263 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 264 #endif 265 266 #ifndef CONFIG_SYS_MONITOR_BASE 267 #ifdef CONFIG_SPL_BUILD 268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 269 #else 270 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 271 #endif 272 #endif 273 274 /* High Level Configuration Options */ 275 #define CONFIG_BOOKE 276 #define CONFIG_E500 277 278 #define CONFIG_MP 279 280 #define CONFIG_FSL_ELBC 281 #define CONFIG_PCI 282 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 283 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 284 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 285 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 286 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 287 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 288 289 #define CONFIG_FSL_LAW 290 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 291 #define CONFIG_ENV_OVERWRITE 292 293 #define CONFIG_CMD_SATA 294 #define CONFIG_SATA_SIL 295 #define CONFIG_SYS_SATA_MAX_DEVICE 2 296 #define CONFIG_LIBATA 297 #define CONFIG_LBA48 298 299 #if defined(CONFIG_P2020RDB) 300 #define CONFIG_SYS_CLK_FREQ 100000000 301 #else 302 #define CONFIG_SYS_CLK_FREQ 66666666 303 #endif 304 #define CONFIG_DDR_CLK_FREQ 66666666 305 306 #define CONFIG_HWCONFIG 307 /* 308 * These can be toggled for performance analysis, otherwise use default. 309 */ 310 #define CONFIG_L2_CACHE 311 #define CONFIG_BTB 312 313 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 314 315 #define CONFIG_ENABLE_36BIT_PHYS 316 317 #ifdef CONFIG_PHYS_64BIT 318 #define CONFIG_ADDR_MAP 1 319 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 320 #endif 321 322 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 323 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 324 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 325 326 #define CONFIG_SYS_CCSRBAR 0xffe00000 327 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 328 329 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 330 SPL code*/ 331 #ifdef CONFIG_SPL_BUILD 332 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 333 #endif 334 335 /* DDR Setup */ 336 #define CONFIG_SYS_FSL_DDR3 337 #define CONFIG_SYS_DDR_RAW_TIMING 338 #define CONFIG_DDR_SPD 339 #define CONFIG_SYS_SPD_BUS_NUM 1 340 #define SPD_EEPROM_ADDRESS 0x52 341 #undef CONFIG_FSL_DDR_INTERACTIVE 342 343 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 344 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 345 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 346 #else 347 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 348 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 349 #endif 350 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 351 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 352 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 353 354 #define CONFIG_NUM_DDR_CONTROLLERS 1 355 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 356 357 /* Default settings for DDR3 */ 358 #ifndef CONFIG_P2020RDB 359 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 360 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 361 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 362 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 363 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 364 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 365 366 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 367 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 368 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 369 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 370 371 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 372 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 373 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 374 #define CONFIG_SYS_DDR_RCW_1 0x00000000 375 #define CONFIG_SYS_DDR_RCW_2 0x00000000 376 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 377 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 378 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 379 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 380 381 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 382 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 383 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 384 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 385 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 386 #define CONFIG_SYS_DDR_MODE_1 0x40461520 387 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 388 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 389 #endif 390 391 #undef CONFIG_CLOCKS_IN_MHZ 392 393 /* 394 * Memory map 395 * 396 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 397 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 398 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 399 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 400 * (early boot only) 401 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 402 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 403 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 404 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 405 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 406 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 407 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 408 */ 409 410 /* 411 * Local Bus Definitions 412 */ 413 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 414 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 415 #define CONFIG_SYS_FLASH_BASE 0xec000000 416 #elif defined(CONFIG_P1020UTM) 417 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 418 #define CONFIG_SYS_FLASH_BASE 0xee000000 419 #else 420 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 421 #define CONFIG_SYS_FLASH_BASE 0xef000000 422 #endif 423 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 426 #else 427 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 428 #endif 429 430 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 431 | BR_PS_16 | BR_V) 432 433 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 434 435 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 436 #define CONFIG_SYS_FLASH_QUIET_TEST 437 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 438 439 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 440 441 #undef CONFIG_SYS_FLASH_CHECKSUM 442 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 443 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 444 445 #define CONFIG_FLASH_CFI_DRIVER 446 #define CONFIG_SYS_FLASH_CFI 447 #define CONFIG_SYS_FLASH_EMPTY_INFO 448 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 449 450 /* Nand Flash */ 451 #ifdef CONFIG_NAND_FSL_ELBC 452 #define CONFIG_SYS_NAND_BASE 0xff800000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 455 #else 456 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 457 #endif 458 459 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 460 #define CONFIG_SYS_MAX_NAND_DEVICE 1 461 #define CONFIG_CMD_NAND 462 #if defined(CONFIG_P1020RDB_PD) 463 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 464 #else 465 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 466 #endif 467 468 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 469 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 470 | BR_PS_8 /* Port Size = 8 bit */ \ 471 | BR_MS_FCM /* MSEL = FCM */ \ 472 | BR_V) /* valid */ 473 #if defined(CONFIG_P1020RDB_PD) 474 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 475 | OR_FCM_PGS /* Large Page*/ \ 476 | OR_FCM_CSCT \ 477 | OR_FCM_CST \ 478 | OR_FCM_CHT \ 479 | OR_FCM_SCY_1 \ 480 | OR_FCM_TRLX \ 481 | OR_FCM_EHTR) 482 #else 483 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 484 | OR_FCM_CSCT \ 485 | OR_FCM_CST \ 486 | OR_FCM_CHT \ 487 | OR_FCM_SCY_1 \ 488 | OR_FCM_TRLX \ 489 | OR_FCM_EHTR) 490 #endif 491 #endif /* CONFIG_NAND_FSL_ELBC */ 492 493 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 494 495 #define CONFIG_SYS_INIT_RAM_LOCK 496 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 499 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 500 /* The assembler doesn't like typecast */ 501 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 502 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 503 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 504 #else 505 /* Initial L1 address */ 506 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 507 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 508 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 509 #endif 510 /* Size of used area in RAM */ 511 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 512 513 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 514 GENERATED_GBL_DATA_SIZE) 515 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 516 517 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 518 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 519 520 #define CONFIG_SYS_CPLD_BASE 0xffa00000 521 #ifdef CONFIG_PHYS_64BIT 522 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 523 #else 524 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 525 #endif 526 /* CPLD config size: 1Mb */ 527 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 528 BR_PS_8 | BR_V) 529 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 530 531 #define CONFIG_SYS_PMC_BASE 0xff980000 532 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 533 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 534 BR_PS_8 | BR_V) 535 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 536 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 537 OR_GPCM_EAD) 538 539 #ifdef CONFIG_NAND 540 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 541 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 542 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 543 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 544 #else 545 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 546 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 547 #ifdef CONFIG_NAND_FSL_ELBC 548 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 549 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 550 #endif 551 #endif 552 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 553 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 554 555 /* Vsc7385 switch */ 556 #ifdef CONFIG_VSC7385_ENET 557 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 558 559 #ifdef CONFIG_PHYS_64BIT 560 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 561 #else 562 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 563 #endif 564 565 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 566 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 567 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 568 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 569 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 570 571 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 572 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 573 574 /* The size of the VSC7385 firmware image */ 575 #define CONFIG_VSC7385_IMAGE_SIZE 8192 576 #endif 577 578 /* 579 * Config the L2 Cache as L2 SRAM 580 */ 581 #if defined(CONFIG_SPL_BUILD) 582 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 583 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 584 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 585 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 586 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 587 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 588 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 589 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 590 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 591 #if defined(CONFIG_P2020RDB) 592 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 593 #else 594 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 595 #endif 596 #elif defined(CONFIG_NAND) 597 #ifdef CONFIG_TPL_BUILD 598 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 599 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 600 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 601 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 602 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 603 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 604 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 605 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 606 #else 607 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 608 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 609 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 610 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 611 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 612 #endif /* CONFIG_TPL_BUILD */ 613 #endif 614 #endif 615 616 /* Serial Port - controlled on board with jumper J8 617 * open - index 2 618 * shorted - index 1 619 */ 620 #define CONFIG_CONS_INDEX 1 621 #undef CONFIG_SERIAL_SOFTWARE_FIFO 622 #define CONFIG_SYS_NS16550_SERIAL 623 #define CONFIG_SYS_NS16550_REG_SIZE 1 624 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 625 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 626 #define CONFIG_NS16550_MIN_FUNCTIONS 627 #endif 628 629 #define CONFIG_SYS_BAUDRATE_TABLE \ 630 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 631 632 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 633 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 634 635 /* I2C */ 636 #define CONFIG_SYS_I2C 637 #define CONFIG_SYS_I2C_FSL 638 #define CONFIG_SYS_FSL_I2C_SPEED 400000 639 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 640 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 641 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 642 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 643 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 644 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 645 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 646 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 647 648 /* 649 * I2C2 EEPROM 650 */ 651 #undef CONFIG_ID_EEPROM 652 653 #define CONFIG_RTC_PT7C4338 654 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 655 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 656 657 /* enable read and write access to EEPROM */ 658 #define CONFIG_CMD_EEPROM 659 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 660 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 661 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 662 663 /* 664 * eSPI - Enhanced SPI 665 */ 666 #define CONFIG_HARD_SPI 667 668 #if defined(CONFIG_SPI_FLASH) 669 #define CONFIG_SF_DEFAULT_SPEED 10000000 670 #define CONFIG_SF_DEFAULT_MODE 0 671 #endif 672 673 #if defined(CONFIG_PCI) 674 /* 675 * General PCI 676 * Memory space is mapped 1-1, but I/O space must start from 0. 677 */ 678 679 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 680 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 681 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 682 #ifdef CONFIG_PHYS_64BIT 683 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 684 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 685 #else 686 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 687 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 688 #endif 689 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 690 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 691 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 692 #ifdef CONFIG_PHYS_64BIT 693 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 694 #else 695 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 696 #endif 697 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 698 699 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 700 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 701 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 702 #ifdef CONFIG_PHYS_64BIT 703 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 704 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 705 #else 706 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 707 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 708 #endif 709 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 710 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 711 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 712 #ifdef CONFIG_PHYS_64BIT 713 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 714 #else 715 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 716 #endif 717 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 718 719 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 720 #define CONFIG_CMD_PCI 721 722 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 723 #define CONFIG_DOS_PARTITION 724 #endif /* CONFIG_PCI */ 725 726 #if defined(CONFIG_TSEC_ENET) 727 #define CONFIG_MII /* MII PHY management */ 728 #define CONFIG_TSEC1 729 #define CONFIG_TSEC1_NAME "eTSEC1" 730 #define CONFIG_TSEC2 731 #define CONFIG_TSEC2_NAME "eTSEC2" 732 #define CONFIG_TSEC3 733 #define CONFIG_TSEC3_NAME "eTSEC3" 734 735 #define TSEC1_PHY_ADDR 2 736 #define TSEC2_PHY_ADDR 0 737 #define TSEC3_PHY_ADDR 1 738 739 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 740 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 741 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 742 743 #define TSEC1_PHYIDX 0 744 #define TSEC2_PHYIDX 0 745 #define TSEC3_PHYIDX 0 746 747 #define CONFIG_ETHPRIME "eTSEC1" 748 749 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 750 751 #define CONFIG_HAS_ETH0 752 #define CONFIG_HAS_ETH1 753 #define CONFIG_HAS_ETH2 754 #endif /* CONFIG_TSEC_ENET */ 755 756 #ifdef CONFIG_QE 757 /* QE microcode/firmware address */ 758 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 759 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 760 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 761 #endif /* CONFIG_QE */ 762 763 #ifdef CONFIG_P1025RDB 764 /* 765 * QE UEC ethernet configuration 766 */ 767 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 768 769 #undef CONFIG_UEC_ETH 770 #define CONFIG_PHY_MODE_NEED_CHANGE 771 772 #define CONFIG_UEC_ETH1 /* ETH1 */ 773 #define CONFIG_HAS_ETH0 774 775 #ifdef CONFIG_UEC_ETH1 776 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 777 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 778 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 779 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 780 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 781 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 782 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 783 #endif /* CONFIG_UEC_ETH1 */ 784 785 #define CONFIG_UEC_ETH5 /* ETH5 */ 786 #define CONFIG_HAS_ETH1 787 788 #ifdef CONFIG_UEC_ETH5 789 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 790 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 791 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 792 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 793 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 794 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 795 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 796 #endif /* CONFIG_UEC_ETH5 */ 797 #endif /* CONFIG_P1025RDB */ 798 799 /* 800 * Environment 801 */ 802 #ifdef CONFIG_SPIFLASH 803 #define CONFIG_ENV_IS_IN_SPI_FLASH 804 #define CONFIG_ENV_SPI_BUS 0 805 #define CONFIG_ENV_SPI_CS 0 806 #define CONFIG_ENV_SPI_MAX_HZ 10000000 807 #define CONFIG_ENV_SPI_MODE 0 808 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 809 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 810 #define CONFIG_ENV_SECT_SIZE 0x10000 811 #elif defined(CONFIG_SDCARD) 812 #define CONFIG_ENV_IS_IN_MMC 813 #define CONFIG_FSL_FIXED_MMC_LOCATION 814 #define CONFIG_ENV_SIZE 0x2000 815 #define CONFIG_SYS_MMC_ENV_DEV 0 816 #elif defined(CONFIG_NAND) 817 #ifdef CONFIG_TPL_BUILD 818 #define CONFIG_ENV_SIZE 0x2000 819 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 820 #else 821 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 822 #endif 823 #define CONFIG_ENV_IS_IN_NAND 824 #define CONFIG_ENV_OFFSET (1024 * 1024) 825 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 826 #elif defined(CONFIG_SYS_RAMBOOT) 827 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 828 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 829 #define CONFIG_ENV_SIZE 0x2000 830 #else 831 #define CONFIG_ENV_IS_IN_FLASH 832 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 833 #define CONFIG_ENV_SIZE 0x2000 834 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 835 #endif 836 837 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 838 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 839 840 /* 841 * Command line configuration. 842 */ 843 #define CONFIG_CMD_IRQ 844 #define CONFIG_CMD_DATE 845 #define CONFIG_CMD_REGINFO 846 847 /* 848 * USB 849 */ 850 #define CONFIG_HAS_FSL_DR_USB 851 852 #if defined(CONFIG_HAS_FSL_DR_USB) 853 #define CONFIG_USB_EHCI 854 855 #ifdef CONFIG_USB_EHCI 856 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 857 #define CONFIG_USB_EHCI_FSL 858 #endif 859 #endif 860 861 #if defined(CONFIG_P1020RDB_PD) 862 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 863 #endif 864 865 #define CONFIG_MMC 866 867 #ifdef CONFIG_MMC 868 #define CONFIG_FSL_ESDHC 869 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 870 #define CONFIG_GENERIC_MMC 871 #endif 872 873 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 874 || defined(CONFIG_FSL_SATA) 875 #define CONFIG_DOS_PARTITION 876 #endif 877 878 #undef CONFIG_WATCHDOG /* watchdog disabled */ 879 880 /* 881 * Miscellaneous configurable options 882 */ 883 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 884 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 885 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 886 #if defined(CONFIG_CMD_KGDB) 887 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 888 #else 889 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 890 #endif 891 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 892 /* Print Buffer Size */ 893 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 894 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 895 896 /* 897 * For booting Linux, the board info and command line data 898 * have to be in the first 64 MB of memory, since this is 899 * the maximum mapped by the Linux kernel during initialization. 900 */ 901 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 902 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 903 904 #if defined(CONFIG_CMD_KGDB) 905 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 906 #endif 907 908 /* 909 * Environment Configuration 910 */ 911 #define CONFIG_HOSTNAME unknown 912 #define CONFIG_ROOTPATH "/opt/nfsroot" 913 #define CONFIG_BOOTFILE "uImage" 914 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 915 916 /* default location for tftp and bootm */ 917 #define CONFIG_LOADADDR 1000000 918 919 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 920 921 #define CONFIG_BAUDRATE 115200 922 923 #ifdef __SW_BOOT_NOR 924 #define __NOR_RST_CMD \ 925 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 926 i2c mw 18 3 __SW_BOOT_MASK 1; reset 927 #endif 928 #ifdef __SW_BOOT_SPI 929 #define __SPI_RST_CMD \ 930 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 931 i2c mw 18 3 __SW_BOOT_MASK 1; reset 932 #endif 933 #ifdef __SW_BOOT_SD 934 #define __SD_RST_CMD \ 935 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 936 i2c mw 18 3 __SW_BOOT_MASK 1; reset 937 #endif 938 #ifdef __SW_BOOT_NAND 939 #define __NAND_RST_CMD \ 940 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 941 i2c mw 18 3 __SW_BOOT_MASK 1; reset 942 #endif 943 #ifdef __SW_BOOT_PCIE 944 #define __PCIE_RST_CMD \ 945 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 946 i2c mw 18 3 __SW_BOOT_MASK 1; reset 947 #endif 948 949 #define CONFIG_EXTRA_ENV_SETTINGS \ 950 "netdev=eth0\0" \ 951 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 952 "loadaddr=1000000\0" \ 953 "bootfile=uImage\0" \ 954 "tftpflash=tftpboot $loadaddr $uboot; " \ 955 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 956 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 957 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 958 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 959 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 960 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 961 "consoledev=ttyS0\0" \ 962 "ramdiskaddr=2000000\0" \ 963 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 964 "fdtaddr=1e00000\0" \ 965 "bdev=sda1\0" \ 966 "jffs2nor=mtdblock3\0" \ 967 "norbootaddr=ef080000\0" \ 968 "norfdtaddr=ef040000\0" \ 969 "jffs2nand=mtdblock9\0" \ 970 "nandbootaddr=100000\0" \ 971 "nandfdtaddr=80000\0" \ 972 "ramdisk_size=120000\0" \ 973 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 974 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 975 __stringify(__NOR_RST_CMD)"\0" \ 976 __stringify(__SPI_RST_CMD)"\0" \ 977 __stringify(__SD_RST_CMD)"\0" \ 978 __stringify(__NAND_RST_CMD)"\0" \ 979 __stringify(__PCIE_RST_CMD)"\0" 980 981 #define CONFIG_NFSBOOTCOMMAND \ 982 "setenv bootargs root=/dev/nfs rw " \ 983 "nfsroot=$serverip:$rootpath " \ 984 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 985 "console=$consoledev,$baudrate $othbootargs;" \ 986 "tftp $loadaddr $bootfile;" \ 987 "tftp $fdtaddr $fdtfile;" \ 988 "bootm $loadaddr - $fdtaddr" 989 990 #define CONFIG_HDBOOT \ 991 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 992 "console=$consoledev,$baudrate $othbootargs;" \ 993 "usb start;" \ 994 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 995 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 996 "bootm $loadaddr - $fdtaddr" 997 998 #define CONFIG_USB_FAT_BOOT \ 999 "setenv bootargs root=/dev/ram rw " \ 1000 "console=$consoledev,$baudrate $othbootargs " \ 1001 "ramdisk_size=$ramdisk_size;" \ 1002 "usb start;" \ 1003 "fatload usb 0:2 $loadaddr $bootfile;" \ 1004 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1005 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1006 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1007 1008 #define CONFIG_USB_EXT2_BOOT \ 1009 "setenv bootargs root=/dev/ram rw " \ 1010 "console=$consoledev,$baudrate $othbootargs " \ 1011 "ramdisk_size=$ramdisk_size;" \ 1012 "usb start;" \ 1013 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1014 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1015 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1016 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1017 1018 #define CONFIG_NORBOOT \ 1019 "setenv bootargs root=/dev/$jffs2nor rw " \ 1020 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1021 "bootm $norbootaddr - $norfdtaddr" 1022 1023 #define CONFIG_RAMBOOTCOMMAND \ 1024 "setenv bootargs root=/dev/ram rw " \ 1025 "console=$consoledev,$baudrate $othbootargs " \ 1026 "ramdisk_size=$ramdisk_size;" \ 1027 "tftp $ramdiskaddr $ramdiskfile;" \ 1028 "tftp $loadaddr $bootfile;" \ 1029 "tftp $fdtaddr $fdtfile;" \ 1030 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1031 1032 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1033 1034 #endif /* __CONFIG_H */ 1035