1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_MTD_DEVICE 74 #define CONFIG_MTD_PARTITIONS 75 #define CONFIG_CMD_MTDPARTS 76 #define CONFIG_FLASH_CFI_MTD 77 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 79 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 80 #endif 81 82 #if defined(CONFIG_TARGET_P1021RDB) 83 #define CONFIG_BOARDNAME "P1021RDB-PC" 84 #define CONFIG_NAND_FSL_ELBC 85 #define CONFIG_P1021 86 #define CONFIG_QE 87 #define CONFIG_VSC7385_ENET 88 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 89 addresses in the LBC */ 90 #define __SW_BOOT_MASK 0x03 91 #define __SW_BOOT_NOR 0x5c 92 #define __SW_BOOT_SPI 0x1c 93 #define __SW_BOOT_SD 0x9c 94 #define __SW_BOOT_NAND 0xec 95 #define __SW_BOOT_PCIE 0x6c 96 #define CONFIG_SYS_L2_SIZE (256 << 10) 97 /* 98 * Dynamic MTD Partition support with mtdparts 99 */ 100 #define CONFIG_MTD_DEVICE 101 #define CONFIG_MTD_PARTITIONS 102 #define CONFIG_CMD_MTDPARTS 103 #define CONFIG_FLASH_CFI_MTD 104 #ifdef CONFIG_PHYS_64BIT 105 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 106 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 107 "256k(dtb),4608k(kernel),9728k(fs)," \ 108 "256k(qe-ucode-firmware),1280k(u-boot)" 109 #else 110 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 111 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 112 "256k(dtb),4608k(kernel),9728k(fs)," \ 113 "256k(qe-ucode-firmware),1280k(u-boot)" 114 #endif 115 #endif 116 117 #if defined(CONFIG_TARGET_P1024RDB) 118 #define CONFIG_BOARDNAME "P1024RDB" 119 #define CONFIG_NAND_FSL_ELBC 120 #define CONFIG_P1024 121 #define CONFIG_SLIC 122 #define __SW_BOOT_MASK 0xf3 123 #define __SW_BOOT_NOR 0x00 124 #define __SW_BOOT_SPI 0x08 125 #define __SW_BOOT_SD 0x04 126 #define __SW_BOOT_NAND 0x0c 127 #define CONFIG_SYS_L2_SIZE (256 << 10) 128 #endif 129 130 #if defined(CONFIG_TARGET_P1025RDB) 131 #define CONFIG_BOARDNAME "P1025RDB" 132 #define CONFIG_NAND_FSL_ELBC 133 #define CONFIG_P1025 134 #define CONFIG_QE 135 #define CONFIG_SLIC 136 137 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 138 addresses in the LBC */ 139 #define __SW_BOOT_MASK 0xf3 140 #define __SW_BOOT_NOR 0x00 141 #define __SW_BOOT_SPI 0x08 142 #define __SW_BOOT_SD 0x04 143 #define __SW_BOOT_NAND 0x0c 144 #define CONFIG_SYS_L2_SIZE (256 << 10) 145 #endif 146 147 #if defined(CONFIG_TARGET_P2020RDB) 148 #define CONFIG_BOARDNAME "P2020RDB-PC" 149 #define CONFIG_NAND_FSL_ELBC 150 #define CONFIG_P2020 151 #define CONFIG_VSC7385_ENET 152 #define __SW_BOOT_MASK 0x03 153 #define __SW_BOOT_NOR 0xc8 154 #define __SW_BOOT_SPI 0x28 155 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 156 #define __SW_BOOT_NAND 0xe8 157 #define __SW_BOOT_PCIE 0xa8 158 #define CONFIG_SYS_L2_SIZE (512 << 10) 159 /* 160 * Dynamic MTD Partition support with mtdparts 161 */ 162 #define CONFIG_MTD_DEVICE 163 #define CONFIG_MTD_PARTITIONS 164 #define CONFIG_CMD_MTDPARTS 165 #define CONFIG_FLASH_CFI_MTD 166 #ifdef CONFIG_PHYS_64BIT 167 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 168 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 169 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 170 #else 171 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 172 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 173 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 174 #endif 175 #endif 176 177 #ifdef CONFIG_SDCARD 178 #define CONFIG_SPL_MMC_MINIMAL 179 #define CONFIG_SPL_FLUSH_IMAGE 180 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 181 #define CONFIG_FSL_LAW /* Use common FSL init code */ 182 #define CONFIG_SYS_TEXT_BASE 0x11001000 183 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 184 #define CONFIG_SPL_PAD_TO 0x20000 185 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 186 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 187 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 188 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 189 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 190 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 191 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 192 #define CONFIG_SPL_MMC_BOOT 193 #ifdef CONFIG_SPL_BUILD 194 #define CONFIG_SPL_COMMON_INIT_DDR 195 #endif 196 #endif 197 198 #ifdef CONFIG_SPIFLASH 199 #define CONFIG_SPL_SPI_FLASH_MINIMAL 200 #define CONFIG_SPL_FLUSH_IMAGE 201 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 202 #define CONFIG_FSL_LAW /* Use common FSL init code */ 203 #define CONFIG_SYS_TEXT_BASE 0x11001000 204 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 205 #define CONFIG_SPL_PAD_TO 0x20000 206 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 207 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 208 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 209 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 210 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 211 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 212 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 213 #define CONFIG_SPL_SPI_BOOT 214 #ifdef CONFIG_SPL_BUILD 215 #define CONFIG_SPL_COMMON_INIT_DDR 216 #endif 217 #endif 218 219 #ifdef CONFIG_NAND 220 #ifdef CONFIG_TPL_BUILD 221 #define CONFIG_SPL_NAND_BOOT 222 #define CONFIG_SPL_FLUSH_IMAGE 223 #define CONFIG_SPL_NAND_INIT 224 #define CONFIG_SPL_COMMON_INIT_DDR 225 #define CONFIG_SPL_MAX_SIZE (128 << 10) 226 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 227 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 228 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 229 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 230 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 231 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 232 #elif defined(CONFIG_SPL_BUILD) 233 #define CONFIG_SPL_INIT_MINIMAL 234 #define CONFIG_SPL_FLUSH_IMAGE 235 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 236 #define CONFIG_SPL_TEXT_BASE 0xff800000 237 #define CONFIG_SPL_MAX_SIZE 4096 238 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 239 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 240 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 241 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 242 #endif /* not CONFIG_TPL_BUILD */ 243 244 #define CONFIG_SPL_PAD_TO 0x20000 245 #define CONFIG_TPL_PAD_TO 0x20000 246 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 247 #define CONFIG_SYS_TEXT_BASE 0x11001000 248 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 249 #endif 250 251 #ifndef CONFIG_SYS_TEXT_BASE 252 #define CONFIG_SYS_TEXT_BASE 0xeff40000 253 #endif 254 255 #ifndef CONFIG_RESET_VECTOR_ADDRESS 256 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 257 #endif 258 259 #ifndef CONFIG_SYS_MONITOR_BASE 260 #ifdef CONFIG_SPL_BUILD 261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 262 #else 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 264 #endif 265 #endif 266 267 /* High Level Configuration Options */ 268 #define CONFIG_BOOKE 269 #define CONFIG_E500 270 271 #define CONFIG_MP 272 273 #define CONFIG_FSL_ELBC 274 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 275 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 276 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 277 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 278 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 279 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 280 281 #define CONFIG_FSL_LAW 282 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 283 #define CONFIG_ENV_OVERWRITE 284 285 #define CONFIG_CMD_SATA 286 #define CONFIG_SATA_SIL 287 #define CONFIG_SYS_SATA_MAX_DEVICE 2 288 #define CONFIG_LIBATA 289 #define CONFIG_LBA48 290 291 #if defined(CONFIG_TARGET_P2020RDB) 292 #define CONFIG_SYS_CLK_FREQ 100000000 293 #else 294 #define CONFIG_SYS_CLK_FREQ 66666666 295 #endif 296 #define CONFIG_DDR_CLK_FREQ 66666666 297 298 #define CONFIG_HWCONFIG 299 /* 300 * These can be toggled for performance analysis, otherwise use default. 301 */ 302 #define CONFIG_L2_CACHE 303 #define CONFIG_BTB 304 305 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 306 307 #define CONFIG_ENABLE_36BIT_PHYS 308 309 #ifdef CONFIG_PHYS_64BIT 310 #define CONFIG_ADDR_MAP 1 311 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 312 #endif 313 314 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 315 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 316 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 317 318 #define CONFIG_SYS_CCSRBAR 0xffe00000 319 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 320 321 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 322 SPL code*/ 323 #ifdef CONFIG_SPL_BUILD 324 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 325 #endif 326 327 /* DDR Setup */ 328 #define CONFIG_SYS_FSL_DDR3 329 #define CONFIG_SYS_DDR_RAW_TIMING 330 #define CONFIG_DDR_SPD 331 #define CONFIG_SYS_SPD_BUS_NUM 1 332 #define SPD_EEPROM_ADDRESS 0x52 333 #undef CONFIG_FSL_DDR_INTERACTIVE 334 335 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 336 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 337 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 338 #else 339 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 340 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 341 #endif 342 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 343 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 344 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 345 346 #define CONFIG_NUM_DDR_CONTROLLERS 1 347 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 348 349 /* Default settings for DDR3 */ 350 #ifndef CONFIG_TARGET_P2020RDB 351 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 352 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 353 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 354 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 355 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 356 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 357 358 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 359 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 360 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 361 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 362 363 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 364 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 365 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 366 #define CONFIG_SYS_DDR_RCW_1 0x00000000 367 #define CONFIG_SYS_DDR_RCW_2 0x00000000 368 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 369 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 370 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 371 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 372 373 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 374 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 375 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 376 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 377 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 378 #define CONFIG_SYS_DDR_MODE_1 0x40461520 379 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 380 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 381 #endif 382 383 #undef CONFIG_CLOCKS_IN_MHZ 384 385 /* 386 * Memory map 387 * 388 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 389 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 390 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 391 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 392 * (early boot only) 393 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 394 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 395 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 396 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 397 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 398 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 399 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 400 */ 401 402 /* 403 * Local Bus Definitions 404 */ 405 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 406 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 407 #define CONFIG_SYS_FLASH_BASE 0xec000000 408 #elif defined(CONFIG_TARGET_P1020UTM) 409 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 410 #define CONFIG_SYS_FLASH_BASE 0xee000000 411 #else 412 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 413 #define CONFIG_SYS_FLASH_BASE 0xef000000 414 #endif 415 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 418 #else 419 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 420 #endif 421 422 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 423 | BR_PS_16 | BR_V) 424 425 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 426 427 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 428 #define CONFIG_SYS_FLASH_QUIET_TEST 429 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 430 431 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 432 433 #undef CONFIG_SYS_FLASH_CHECKSUM 434 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 435 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 436 437 #define CONFIG_FLASH_CFI_DRIVER 438 #define CONFIG_SYS_FLASH_CFI 439 #define CONFIG_SYS_FLASH_EMPTY_INFO 440 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 441 442 /* Nand Flash */ 443 #ifdef CONFIG_NAND_FSL_ELBC 444 #define CONFIG_SYS_NAND_BASE 0xff800000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 447 #else 448 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 449 #endif 450 451 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 452 #define CONFIG_SYS_MAX_NAND_DEVICE 1 453 #define CONFIG_CMD_NAND 454 #if defined(CONFIG_TARGET_P1020RDB_PD) 455 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 456 #else 457 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 458 #endif 459 460 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 461 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 462 | BR_PS_8 /* Port Size = 8 bit */ \ 463 | BR_MS_FCM /* MSEL = FCM */ \ 464 | BR_V) /* valid */ 465 #if defined(CONFIG_TARGET_P1020RDB_PD) 466 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 467 | OR_FCM_PGS /* Large Page*/ \ 468 | OR_FCM_CSCT \ 469 | OR_FCM_CST \ 470 | OR_FCM_CHT \ 471 | OR_FCM_SCY_1 \ 472 | OR_FCM_TRLX \ 473 | OR_FCM_EHTR) 474 #else 475 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 476 | OR_FCM_CSCT \ 477 | OR_FCM_CST \ 478 | OR_FCM_CHT \ 479 | OR_FCM_SCY_1 \ 480 | OR_FCM_TRLX \ 481 | OR_FCM_EHTR) 482 #endif 483 #endif /* CONFIG_NAND_FSL_ELBC */ 484 485 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 486 487 #define CONFIG_SYS_INIT_RAM_LOCK 488 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 492 /* The assembler doesn't like typecast */ 493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 494 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 495 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 496 #else 497 /* Initial L1 address */ 498 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 499 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 500 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 501 #endif 502 /* Size of used area in RAM */ 503 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 504 505 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 506 GENERATED_GBL_DATA_SIZE) 507 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 508 509 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 510 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 511 512 #define CONFIG_SYS_CPLD_BASE 0xffa00000 513 #ifdef CONFIG_PHYS_64BIT 514 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 515 #else 516 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 517 #endif 518 /* CPLD config size: 1Mb */ 519 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 520 BR_PS_8 | BR_V) 521 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 522 523 #define CONFIG_SYS_PMC_BASE 0xff980000 524 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 525 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 526 BR_PS_8 | BR_V) 527 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 528 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 529 OR_GPCM_EAD) 530 531 #ifdef CONFIG_NAND 532 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 533 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 534 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 535 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 536 #else 537 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 538 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 539 #ifdef CONFIG_NAND_FSL_ELBC 540 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 541 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 542 #endif 543 #endif 544 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 545 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 546 547 /* Vsc7385 switch */ 548 #ifdef CONFIG_VSC7385_ENET 549 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 550 551 #ifdef CONFIG_PHYS_64BIT 552 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 553 #else 554 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 555 #endif 556 557 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 558 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 559 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 560 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 561 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 562 563 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 564 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 565 566 /* The size of the VSC7385 firmware image */ 567 #define CONFIG_VSC7385_IMAGE_SIZE 8192 568 #endif 569 570 /* 571 * Config the L2 Cache as L2 SRAM 572 */ 573 #if defined(CONFIG_SPL_BUILD) 574 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 575 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 576 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 577 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 578 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 579 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 580 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 581 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 582 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 583 #if defined(CONFIG_TARGET_P2020RDB) 584 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 585 #else 586 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 587 #endif 588 #elif defined(CONFIG_NAND) 589 #ifdef CONFIG_TPL_BUILD 590 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 591 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 592 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 593 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 594 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 595 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 596 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 597 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 598 #else 599 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 600 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 601 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 602 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 603 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 604 #endif /* CONFIG_TPL_BUILD */ 605 #endif 606 #endif 607 608 /* Serial Port - controlled on board with jumper J8 609 * open - index 2 610 * shorted - index 1 611 */ 612 #define CONFIG_CONS_INDEX 1 613 #undef CONFIG_SERIAL_SOFTWARE_FIFO 614 #define CONFIG_SYS_NS16550_SERIAL 615 #define CONFIG_SYS_NS16550_REG_SIZE 1 616 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 617 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 618 #define CONFIG_NS16550_MIN_FUNCTIONS 619 #endif 620 621 #define CONFIG_SYS_BAUDRATE_TABLE \ 622 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 623 624 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 625 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 626 627 /* I2C */ 628 #define CONFIG_SYS_I2C 629 #define CONFIG_SYS_I2C_FSL 630 #define CONFIG_SYS_FSL_I2C_SPEED 400000 631 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 632 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 633 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 634 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 635 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 636 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 637 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 638 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 639 640 /* 641 * I2C2 EEPROM 642 */ 643 #undef CONFIG_ID_EEPROM 644 645 #define CONFIG_RTC_PT7C4338 646 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 647 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 648 649 /* enable read and write access to EEPROM */ 650 #define CONFIG_CMD_EEPROM 651 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 652 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 653 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 654 655 /* 656 * eSPI - Enhanced SPI 657 */ 658 #define CONFIG_HARD_SPI 659 660 #if defined(CONFIG_SPI_FLASH) 661 #define CONFIG_SF_DEFAULT_SPEED 10000000 662 #define CONFIG_SF_DEFAULT_MODE 0 663 #endif 664 665 #if defined(CONFIG_PCI) 666 /* 667 * General PCI 668 * Memory space is mapped 1-1, but I/O space must start from 0. 669 */ 670 671 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 672 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 673 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 674 #ifdef CONFIG_PHYS_64BIT 675 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 676 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 677 #else 678 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 679 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 680 #endif 681 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 682 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 683 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 684 #ifdef CONFIG_PHYS_64BIT 685 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 686 #else 687 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 688 #endif 689 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 690 691 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 692 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 693 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 694 #ifdef CONFIG_PHYS_64BIT 695 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 696 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 697 #else 698 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 699 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 700 #endif 701 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 702 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 703 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 704 #ifdef CONFIG_PHYS_64BIT 705 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 706 #else 707 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 708 #endif 709 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 710 711 #define CONFIG_CMD_PCI 712 713 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 714 #define CONFIG_DOS_PARTITION 715 #endif /* CONFIG_PCI */ 716 717 #if defined(CONFIG_TSEC_ENET) 718 #define CONFIG_MII /* MII PHY management */ 719 #define CONFIG_TSEC1 720 #define CONFIG_TSEC1_NAME "eTSEC1" 721 #define CONFIG_TSEC2 722 #define CONFIG_TSEC2_NAME "eTSEC2" 723 #define CONFIG_TSEC3 724 #define CONFIG_TSEC3_NAME "eTSEC3" 725 726 #define TSEC1_PHY_ADDR 2 727 #define TSEC2_PHY_ADDR 0 728 #define TSEC3_PHY_ADDR 1 729 730 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 731 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 732 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 733 734 #define TSEC1_PHYIDX 0 735 #define TSEC2_PHYIDX 0 736 #define TSEC3_PHYIDX 0 737 738 #define CONFIG_ETHPRIME "eTSEC1" 739 740 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 741 742 #define CONFIG_HAS_ETH0 743 #define CONFIG_HAS_ETH1 744 #define CONFIG_HAS_ETH2 745 #endif /* CONFIG_TSEC_ENET */ 746 747 #ifdef CONFIG_QE 748 /* QE microcode/firmware address */ 749 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 750 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 751 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 752 #endif /* CONFIG_QE */ 753 754 #ifdef CONFIG_TARGET_P1025RDB 755 /* 756 * QE UEC ethernet configuration 757 */ 758 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 759 760 #undef CONFIG_UEC_ETH 761 #define CONFIG_PHY_MODE_NEED_CHANGE 762 763 #define CONFIG_UEC_ETH1 /* ETH1 */ 764 #define CONFIG_HAS_ETH0 765 766 #ifdef CONFIG_UEC_ETH1 767 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 768 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 769 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 770 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 771 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 772 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 773 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 774 #endif /* CONFIG_UEC_ETH1 */ 775 776 #define CONFIG_UEC_ETH5 /* ETH5 */ 777 #define CONFIG_HAS_ETH1 778 779 #ifdef CONFIG_UEC_ETH5 780 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 781 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 782 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 783 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 784 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 785 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 786 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 787 #endif /* CONFIG_UEC_ETH5 */ 788 #endif /* CONFIG_TARGET_P1025RDB */ 789 790 /* 791 * Environment 792 */ 793 #ifdef CONFIG_SPIFLASH 794 #define CONFIG_ENV_IS_IN_SPI_FLASH 795 #define CONFIG_ENV_SPI_BUS 0 796 #define CONFIG_ENV_SPI_CS 0 797 #define CONFIG_ENV_SPI_MAX_HZ 10000000 798 #define CONFIG_ENV_SPI_MODE 0 799 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 800 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 801 #define CONFIG_ENV_SECT_SIZE 0x10000 802 #elif defined(CONFIG_SDCARD) 803 #define CONFIG_ENV_IS_IN_MMC 804 #define CONFIG_FSL_FIXED_MMC_LOCATION 805 #define CONFIG_ENV_SIZE 0x2000 806 #define CONFIG_SYS_MMC_ENV_DEV 0 807 #elif defined(CONFIG_NAND) 808 #ifdef CONFIG_TPL_BUILD 809 #define CONFIG_ENV_SIZE 0x2000 810 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 811 #else 812 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 813 #endif 814 #define CONFIG_ENV_IS_IN_NAND 815 #define CONFIG_ENV_OFFSET (1024 * 1024) 816 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 817 #elif defined(CONFIG_SYS_RAMBOOT) 818 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 819 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 820 #define CONFIG_ENV_SIZE 0x2000 821 #else 822 #define CONFIG_ENV_IS_IN_FLASH 823 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 824 #define CONFIG_ENV_SIZE 0x2000 825 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 826 #endif 827 828 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 829 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 830 831 /* 832 * Command line configuration. 833 */ 834 #define CONFIG_CMD_IRQ 835 #define CONFIG_CMD_DATE 836 #define CONFIG_CMD_REGINFO 837 838 /* 839 * USB 840 */ 841 #define CONFIG_HAS_FSL_DR_USB 842 843 #if defined(CONFIG_HAS_FSL_DR_USB) 844 #define CONFIG_USB_EHCI 845 846 #ifdef CONFIG_USB_EHCI 847 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 848 #define CONFIG_USB_EHCI_FSL 849 #endif 850 #endif 851 852 #if defined(CONFIG_TARGET_P1020RDB_PD) 853 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 854 #endif 855 856 #define CONFIG_MMC 857 858 #ifdef CONFIG_MMC 859 #define CONFIG_FSL_ESDHC 860 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 861 #define CONFIG_GENERIC_MMC 862 #endif 863 864 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 865 || defined(CONFIG_FSL_SATA) 866 #define CONFIG_DOS_PARTITION 867 #endif 868 869 #undef CONFIG_WATCHDOG /* watchdog disabled */ 870 871 /* 872 * Miscellaneous configurable options 873 */ 874 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 875 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 876 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 877 #if defined(CONFIG_CMD_KGDB) 878 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 879 #else 880 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 881 #endif 882 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 883 /* Print Buffer Size */ 884 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 885 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 886 887 /* 888 * For booting Linux, the board info and command line data 889 * have to be in the first 64 MB of memory, since this is 890 * the maximum mapped by the Linux kernel during initialization. 891 */ 892 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 893 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 894 895 #if defined(CONFIG_CMD_KGDB) 896 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 897 #endif 898 899 /* 900 * Environment Configuration 901 */ 902 #define CONFIG_HOSTNAME unknown 903 #define CONFIG_ROOTPATH "/opt/nfsroot" 904 #define CONFIG_BOOTFILE "uImage" 905 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 906 907 /* default location for tftp and bootm */ 908 #define CONFIG_LOADADDR 1000000 909 910 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 911 912 #define CONFIG_BAUDRATE 115200 913 914 #ifdef __SW_BOOT_NOR 915 #define __NOR_RST_CMD \ 916 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 917 i2c mw 18 3 __SW_BOOT_MASK 1; reset 918 #endif 919 #ifdef __SW_BOOT_SPI 920 #define __SPI_RST_CMD \ 921 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 922 i2c mw 18 3 __SW_BOOT_MASK 1; reset 923 #endif 924 #ifdef __SW_BOOT_SD 925 #define __SD_RST_CMD \ 926 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 927 i2c mw 18 3 __SW_BOOT_MASK 1; reset 928 #endif 929 #ifdef __SW_BOOT_NAND 930 #define __NAND_RST_CMD \ 931 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 932 i2c mw 18 3 __SW_BOOT_MASK 1; reset 933 #endif 934 #ifdef __SW_BOOT_PCIE 935 #define __PCIE_RST_CMD \ 936 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 937 i2c mw 18 3 __SW_BOOT_MASK 1; reset 938 #endif 939 940 #define CONFIG_EXTRA_ENV_SETTINGS \ 941 "netdev=eth0\0" \ 942 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 943 "loadaddr=1000000\0" \ 944 "bootfile=uImage\0" \ 945 "tftpflash=tftpboot $loadaddr $uboot; " \ 946 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 947 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 948 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 949 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 950 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 951 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 952 "consoledev=ttyS0\0" \ 953 "ramdiskaddr=2000000\0" \ 954 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 955 "fdtaddr=1e00000\0" \ 956 "bdev=sda1\0" \ 957 "jffs2nor=mtdblock3\0" \ 958 "norbootaddr=ef080000\0" \ 959 "norfdtaddr=ef040000\0" \ 960 "jffs2nand=mtdblock9\0" \ 961 "nandbootaddr=100000\0" \ 962 "nandfdtaddr=80000\0" \ 963 "ramdisk_size=120000\0" \ 964 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 965 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 966 __stringify(__NOR_RST_CMD)"\0" \ 967 __stringify(__SPI_RST_CMD)"\0" \ 968 __stringify(__SD_RST_CMD)"\0" \ 969 __stringify(__NAND_RST_CMD)"\0" \ 970 __stringify(__PCIE_RST_CMD)"\0" 971 972 #define CONFIG_NFSBOOTCOMMAND \ 973 "setenv bootargs root=/dev/nfs rw " \ 974 "nfsroot=$serverip:$rootpath " \ 975 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 976 "console=$consoledev,$baudrate $othbootargs;" \ 977 "tftp $loadaddr $bootfile;" \ 978 "tftp $fdtaddr $fdtfile;" \ 979 "bootm $loadaddr - $fdtaddr" 980 981 #define CONFIG_HDBOOT \ 982 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 983 "console=$consoledev,$baudrate $othbootargs;" \ 984 "usb start;" \ 985 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 986 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 987 "bootm $loadaddr - $fdtaddr" 988 989 #define CONFIG_USB_FAT_BOOT \ 990 "setenv bootargs root=/dev/ram rw " \ 991 "console=$consoledev,$baudrate $othbootargs " \ 992 "ramdisk_size=$ramdisk_size;" \ 993 "usb start;" \ 994 "fatload usb 0:2 $loadaddr $bootfile;" \ 995 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 996 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 997 "bootm $loadaddr $ramdiskaddr $fdtaddr" 998 999 #define CONFIG_USB_EXT2_BOOT \ 1000 "setenv bootargs root=/dev/ram rw " \ 1001 "console=$consoledev,$baudrate $othbootargs " \ 1002 "ramdisk_size=$ramdisk_size;" \ 1003 "usb start;" \ 1004 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1005 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1006 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1007 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1008 1009 #define CONFIG_NORBOOT \ 1010 "setenv bootargs root=/dev/$jffs2nor rw " \ 1011 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1012 "bootm $norbootaddr - $norfdtaddr" 1013 1014 #define CONFIG_RAMBOOTCOMMAND \ 1015 "setenv bootargs root=/dev/ram rw " \ 1016 "console=$consoledev,$baudrate $othbootargs " \ 1017 "ramdisk_size=$ramdisk_size;" \ 1018 "tftp $ramdiskaddr $ramdiskfile;" \ 1019 "tftp $loadaddr $bootfile;" \ 1020 "tftp $fdtaddr $fdtfile;" \ 1021 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1022 1023 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1024 1025 #endif /* __CONFIG_H */ 1026