1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_MTD_DEVICE 74 #define CONFIG_MTD_PARTITIONS 75 #define CONFIG_CMD_MTDPARTS 76 #define CONFIG_FLASH_CFI_MTD 77 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 79 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 80 #endif 81 82 #if defined(CONFIG_TARGET_P1021RDB) 83 #define CONFIG_BOARDNAME "P1021RDB-PC" 84 #define CONFIG_NAND_FSL_ELBC 85 #define CONFIG_QE 86 #define CONFIG_VSC7385_ENET 87 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 88 addresses in the LBC */ 89 #define __SW_BOOT_MASK 0x03 90 #define __SW_BOOT_NOR 0x5c 91 #define __SW_BOOT_SPI 0x1c 92 #define __SW_BOOT_SD 0x9c 93 #define __SW_BOOT_NAND 0xec 94 #define __SW_BOOT_PCIE 0x6c 95 #define CONFIG_SYS_L2_SIZE (256 << 10) 96 /* 97 * Dynamic MTD Partition support with mtdparts 98 */ 99 #define CONFIG_MTD_DEVICE 100 #define CONFIG_MTD_PARTITIONS 101 #define CONFIG_CMD_MTDPARTS 102 #define CONFIG_FLASH_CFI_MTD 103 #ifdef CONFIG_PHYS_64BIT 104 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 106 "256k(dtb),4608k(kernel),9728k(fs)," \ 107 "256k(qe-ucode-firmware),1280k(u-boot)" 108 #else 109 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 111 "256k(dtb),4608k(kernel),9728k(fs)," \ 112 "256k(qe-ucode-firmware),1280k(u-boot)" 113 #endif 114 #endif 115 116 #if defined(CONFIG_TARGET_P1024RDB) 117 #define CONFIG_BOARDNAME "P1024RDB" 118 #define CONFIG_NAND_FSL_ELBC 119 #define CONFIG_SLIC 120 #define __SW_BOOT_MASK 0xf3 121 #define __SW_BOOT_NOR 0x00 122 #define __SW_BOOT_SPI 0x08 123 #define __SW_BOOT_SD 0x04 124 #define __SW_BOOT_NAND 0x0c 125 #define CONFIG_SYS_L2_SIZE (256 << 10) 126 #endif 127 128 #if defined(CONFIG_TARGET_P1025RDB) 129 #define CONFIG_BOARDNAME "P1025RDB" 130 #define CONFIG_NAND_FSL_ELBC 131 #define CONFIG_QE 132 #define CONFIG_SLIC 133 134 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 135 addresses in the LBC */ 136 #define __SW_BOOT_MASK 0xf3 137 #define __SW_BOOT_NOR 0x00 138 #define __SW_BOOT_SPI 0x08 139 #define __SW_BOOT_SD 0x04 140 #define __SW_BOOT_NAND 0x0c 141 #define CONFIG_SYS_L2_SIZE (256 << 10) 142 #endif 143 144 #if defined(CONFIG_TARGET_P2020RDB) 145 #define CONFIG_BOARDNAME "P2020RDB-PC" 146 #define CONFIG_NAND_FSL_ELBC 147 #define CONFIG_P2020 148 #define CONFIG_VSC7385_ENET 149 #define __SW_BOOT_MASK 0x03 150 #define __SW_BOOT_NOR 0xc8 151 #define __SW_BOOT_SPI 0x28 152 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 153 #define __SW_BOOT_NAND 0xe8 154 #define __SW_BOOT_PCIE 0xa8 155 #define CONFIG_SYS_L2_SIZE (512 << 10) 156 /* 157 * Dynamic MTD Partition support with mtdparts 158 */ 159 #define CONFIG_MTD_DEVICE 160 #define CONFIG_MTD_PARTITIONS 161 #define CONFIG_CMD_MTDPARTS 162 #define CONFIG_FLASH_CFI_MTD 163 #ifdef CONFIG_PHYS_64BIT 164 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 165 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 166 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 167 #else 168 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 169 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 170 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 171 #endif 172 #endif 173 174 #ifdef CONFIG_SDCARD 175 #define CONFIG_SPL_MMC_MINIMAL 176 #define CONFIG_SPL_FLUSH_IMAGE 177 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 178 #define CONFIG_FSL_LAW /* Use common FSL init code */ 179 #define CONFIG_SYS_TEXT_BASE 0x11001000 180 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 181 #define CONFIG_SPL_PAD_TO 0x20000 182 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 183 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 184 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 185 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 186 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 187 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 188 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 189 #define CONFIG_SPL_MMC_BOOT 190 #ifdef CONFIG_SPL_BUILD 191 #define CONFIG_SPL_COMMON_INIT_DDR 192 #endif 193 #endif 194 195 #ifdef CONFIG_SPIFLASH 196 #define CONFIG_SPL_SPI_FLASH_MINIMAL 197 #define CONFIG_SPL_FLUSH_IMAGE 198 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 199 #define CONFIG_FSL_LAW /* Use common FSL init code */ 200 #define CONFIG_SYS_TEXT_BASE 0x11001000 201 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 202 #define CONFIG_SPL_PAD_TO 0x20000 203 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 204 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 205 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 206 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 207 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 208 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 209 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 210 #define CONFIG_SPL_SPI_BOOT 211 #ifdef CONFIG_SPL_BUILD 212 #define CONFIG_SPL_COMMON_INIT_DDR 213 #endif 214 #endif 215 216 #ifdef CONFIG_NAND 217 #ifdef CONFIG_TPL_BUILD 218 #define CONFIG_SPL_NAND_BOOT 219 #define CONFIG_SPL_FLUSH_IMAGE 220 #define CONFIG_SPL_NAND_INIT 221 #define CONFIG_SPL_COMMON_INIT_DDR 222 #define CONFIG_SPL_MAX_SIZE (128 << 10) 223 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 224 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 225 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 226 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 227 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 229 #elif defined(CONFIG_SPL_BUILD) 230 #define CONFIG_SPL_INIT_MINIMAL 231 #define CONFIG_SPL_FLUSH_IMAGE 232 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 233 #define CONFIG_SPL_TEXT_BASE 0xff800000 234 #define CONFIG_SPL_MAX_SIZE 4096 235 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 236 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 237 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 238 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 239 #endif /* not CONFIG_TPL_BUILD */ 240 241 #define CONFIG_SPL_PAD_TO 0x20000 242 #define CONFIG_TPL_PAD_TO 0x20000 243 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 244 #define CONFIG_SYS_TEXT_BASE 0x11001000 245 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 246 #endif 247 248 #ifndef CONFIG_SYS_TEXT_BASE 249 #define CONFIG_SYS_TEXT_BASE 0xeff40000 250 #endif 251 252 #ifndef CONFIG_RESET_VECTOR_ADDRESS 253 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 254 #endif 255 256 #ifndef CONFIG_SYS_MONITOR_BASE 257 #ifdef CONFIG_SPL_BUILD 258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 259 #else 260 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 261 #endif 262 #endif 263 264 /* High Level Configuration Options */ 265 #define CONFIG_BOOKE 266 #define CONFIG_E500 267 268 #define CONFIG_MP 269 270 #define CONFIG_FSL_ELBC 271 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 272 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 273 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 274 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 275 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 276 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 277 278 #define CONFIG_FSL_LAW 279 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 280 #define CONFIG_ENV_OVERWRITE 281 282 #define CONFIG_CMD_SATA 283 #define CONFIG_SATA_SIL 284 #define CONFIG_SYS_SATA_MAX_DEVICE 2 285 #define CONFIG_LIBATA 286 #define CONFIG_LBA48 287 288 #if defined(CONFIG_TARGET_P2020RDB) 289 #define CONFIG_SYS_CLK_FREQ 100000000 290 #else 291 #define CONFIG_SYS_CLK_FREQ 66666666 292 #endif 293 #define CONFIG_DDR_CLK_FREQ 66666666 294 295 #define CONFIG_HWCONFIG 296 /* 297 * These can be toggled for performance analysis, otherwise use default. 298 */ 299 #define CONFIG_L2_CACHE 300 #define CONFIG_BTB 301 302 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 303 304 #define CONFIG_ENABLE_36BIT_PHYS 305 306 #ifdef CONFIG_PHYS_64BIT 307 #define CONFIG_ADDR_MAP 1 308 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 309 #endif 310 311 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 312 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 313 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 314 315 #define CONFIG_SYS_CCSRBAR 0xffe00000 316 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 317 318 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 319 SPL code*/ 320 #ifdef CONFIG_SPL_BUILD 321 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 322 #endif 323 324 /* DDR Setup */ 325 #define CONFIG_SYS_FSL_DDR3 326 #define CONFIG_SYS_DDR_RAW_TIMING 327 #define CONFIG_DDR_SPD 328 #define CONFIG_SYS_SPD_BUS_NUM 1 329 #define SPD_EEPROM_ADDRESS 0x52 330 #undef CONFIG_FSL_DDR_INTERACTIVE 331 332 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 333 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 334 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 335 #else 336 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 337 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 338 #endif 339 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 340 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 341 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 342 343 #define CONFIG_NUM_DDR_CONTROLLERS 1 344 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 345 346 /* Default settings for DDR3 */ 347 #ifndef CONFIG_TARGET_P2020RDB 348 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 349 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 350 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 351 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 352 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 353 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 354 355 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 356 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 357 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 358 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 359 360 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 361 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 362 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 363 #define CONFIG_SYS_DDR_RCW_1 0x00000000 364 #define CONFIG_SYS_DDR_RCW_2 0x00000000 365 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 366 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 367 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 368 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 369 370 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 371 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 372 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 373 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 374 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 375 #define CONFIG_SYS_DDR_MODE_1 0x40461520 376 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 377 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 378 #endif 379 380 #undef CONFIG_CLOCKS_IN_MHZ 381 382 /* 383 * Memory map 384 * 385 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 386 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 387 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 388 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 389 * (early boot only) 390 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 391 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 392 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 393 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 394 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 395 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 396 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 397 */ 398 399 /* 400 * Local Bus Definitions 401 */ 402 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 403 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 404 #define CONFIG_SYS_FLASH_BASE 0xec000000 405 #elif defined(CONFIG_TARGET_P1020UTM) 406 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 407 #define CONFIG_SYS_FLASH_BASE 0xee000000 408 #else 409 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 410 #define CONFIG_SYS_FLASH_BASE 0xef000000 411 #endif 412 413 #ifdef CONFIG_PHYS_64BIT 414 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 415 #else 416 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 417 #endif 418 419 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 420 | BR_PS_16 | BR_V) 421 422 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 423 424 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 425 #define CONFIG_SYS_FLASH_QUIET_TEST 426 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 427 428 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 429 430 #undef CONFIG_SYS_FLASH_CHECKSUM 431 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 432 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 433 434 #define CONFIG_FLASH_CFI_DRIVER 435 #define CONFIG_SYS_FLASH_CFI 436 #define CONFIG_SYS_FLASH_EMPTY_INFO 437 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 438 439 /* Nand Flash */ 440 #ifdef CONFIG_NAND_FSL_ELBC 441 #define CONFIG_SYS_NAND_BASE 0xff800000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 444 #else 445 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 446 #endif 447 448 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 449 #define CONFIG_SYS_MAX_NAND_DEVICE 1 450 #define CONFIG_CMD_NAND 451 #if defined(CONFIG_TARGET_P1020RDB_PD) 452 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 453 #else 454 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 455 #endif 456 457 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 458 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 459 | BR_PS_8 /* Port Size = 8 bit */ \ 460 | BR_MS_FCM /* MSEL = FCM */ \ 461 | BR_V) /* valid */ 462 #if defined(CONFIG_TARGET_P1020RDB_PD) 463 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 464 | OR_FCM_PGS /* Large Page*/ \ 465 | OR_FCM_CSCT \ 466 | OR_FCM_CST \ 467 | OR_FCM_CHT \ 468 | OR_FCM_SCY_1 \ 469 | OR_FCM_TRLX \ 470 | OR_FCM_EHTR) 471 #else 472 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 473 | OR_FCM_CSCT \ 474 | OR_FCM_CST \ 475 | OR_FCM_CHT \ 476 | OR_FCM_SCY_1 \ 477 | OR_FCM_TRLX \ 478 | OR_FCM_EHTR) 479 #endif 480 #endif /* CONFIG_NAND_FSL_ELBC */ 481 482 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 483 484 #define CONFIG_SYS_INIT_RAM_LOCK 485 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 486 #ifdef CONFIG_PHYS_64BIT 487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 488 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 489 /* The assembler doesn't like typecast */ 490 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 491 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 492 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 493 #else 494 /* Initial L1 address */ 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 496 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 497 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 498 #endif 499 /* Size of used area in RAM */ 500 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 501 502 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 503 GENERATED_GBL_DATA_SIZE) 504 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 505 506 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 507 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 508 509 #define CONFIG_SYS_CPLD_BASE 0xffa00000 510 #ifdef CONFIG_PHYS_64BIT 511 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 512 #else 513 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 514 #endif 515 /* CPLD config size: 1Mb */ 516 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 517 BR_PS_8 | BR_V) 518 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 519 520 #define CONFIG_SYS_PMC_BASE 0xff980000 521 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 522 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 523 BR_PS_8 | BR_V) 524 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 525 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 526 OR_GPCM_EAD) 527 528 #ifdef CONFIG_NAND 529 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 530 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 531 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 532 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 533 #else 534 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 535 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 536 #ifdef CONFIG_NAND_FSL_ELBC 537 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 538 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 539 #endif 540 #endif 541 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 542 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 543 544 /* Vsc7385 switch */ 545 #ifdef CONFIG_VSC7385_ENET 546 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 547 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 550 #else 551 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 552 #endif 553 554 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 555 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 556 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 557 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 558 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 559 560 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 561 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 562 563 /* The size of the VSC7385 firmware image */ 564 #define CONFIG_VSC7385_IMAGE_SIZE 8192 565 #endif 566 567 /* 568 * Config the L2 Cache as L2 SRAM 569 */ 570 #if defined(CONFIG_SPL_BUILD) 571 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 572 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 573 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 574 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 575 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 576 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 577 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 578 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 579 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 580 #if defined(CONFIG_TARGET_P2020RDB) 581 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 582 #else 583 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 584 #endif 585 #elif defined(CONFIG_NAND) 586 #ifdef CONFIG_TPL_BUILD 587 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 588 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 589 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 590 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 591 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 592 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 593 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 594 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 595 #else 596 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 597 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 598 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 599 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 600 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 601 #endif /* CONFIG_TPL_BUILD */ 602 #endif 603 #endif 604 605 /* Serial Port - controlled on board with jumper J8 606 * open - index 2 607 * shorted - index 1 608 */ 609 #define CONFIG_CONS_INDEX 1 610 #undef CONFIG_SERIAL_SOFTWARE_FIFO 611 #define CONFIG_SYS_NS16550_SERIAL 612 #define CONFIG_SYS_NS16550_REG_SIZE 1 613 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 614 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 615 #define CONFIG_NS16550_MIN_FUNCTIONS 616 #endif 617 618 #define CONFIG_SYS_BAUDRATE_TABLE \ 619 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 620 621 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 622 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 623 624 /* I2C */ 625 #define CONFIG_SYS_I2C 626 #define CONFIG_SYS_I2C_FSL 627 #define CONFIG_SYS_FSL_I2C_SPEED 400000 628 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 629 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 630 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 631 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 632 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 633 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 634 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 635 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 636 637 /* 638 * I2C2 EEPROM 639 */ 640 #undef CONFIG_ID_EEPROM 641 642 #define CONFIG_RTC_PT7C4338 643 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 644 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 645 646 /* enable read and write access to EEPROM */ 647 #define CONFIG_CMD_EEPROM 648 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 649 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 650 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 651 652 /* 653 * eSPI - Enhanced SPI 654 */ 655 #define CONFIG_HARD_SPI 656 657 #if defined(CONFIG_SPI_FLASH) 658 #define CONFIG_SF_DEFAULT_SPEED 10000000 659 #define CONFIG_SF_DEFAULT_MODE 0 660 #endif 661 662 #if defined(CONFIG_PCI) 663 /* 664 * General PCI 665 * Memory space is mapped 1-1, but I/O space must start from 0. 666 */ 667 668 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 669 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 670 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 671 #ifdef CONFIG_PHYS_64BIT 672 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 673 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 674 #else 675 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 676 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 677 #endif 678 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 679 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 680 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 681 #ifdef CONFIG_PHYS_64BIT 682 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 683 #else 684 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 685 #endif 686 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 687 688 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 689 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 690 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 691 #ifdef CONFIG_PHYS_64BIT 692 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 693 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 694 #else 695 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 696 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 697 #endif 698 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 699 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 700 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 701 #ifdef CONFIG_PHYS_64BIT 702 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 703 #else 704 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 705 #endif 706 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 707 708 #define CONFIG_CMD_PCI 709 710 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 711 #define CONFIG_DOS_PARTITION 712 #endif /* CONFIG_PCI */ 713 714 #if defined(CONFIG_TSEC_ENET) 715 #define CONFIG_MII /* MII PHY management */ 716 #define CONFIG_TSEC1 717 #define CONFIG_TSEC1_NAME "eTSEC1" 718 #define CONFIG_TSEC2 719 #define CONFIG_TSEC2_NAME "eTSEC2" 720 #define CONFIG_TSEC3 721 #define CONFIG_TSEC3_NAME "eTSEC3" 722 723 #define TSEC1_PHY_ADDR 2 724 #define TSEC2_PHY_ADDR 0 725 #define TSEC3_PHY_ADDR 1 726 727 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 728 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 729 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 730 731 #define TSEC1_PHYIDX 0 732 #define TSEC2_PHYIDX 0 733 #define TSEC3_PHYIDX 0 734 735 #define CONFIG_ETHPRIME "eTSEC1" 736 737 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 738 739 #define CONFIG_HAS_ETH0 740 #define CONFIG_HAS_ETH1 741 #define CONFIG_HAS_ETH2 742 #endif /* CONFIG_TSEC_ENET */ 743 744 #ifdef CONFIG_QE 745 /* QE microcode/firmware address */ 746 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 747 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 748 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 749 #endif /* CONFIG_QE */ 750 751 #ifdef CONFIG_TARGET_P1025RDB 752 /* 753 * QE UEC ethernet configuration 754 */ 755 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 756 757 #undef CONFIG_UEC_ETH 758 #define CONFIG_PHY_MODE_NEED_CHANGE 759 760 #define CONFIG_UEC_ETH1 /* ETH1 */ 761 #define CONFIG_HAS_ETH0 762 763 #ifdef CONFIG_UEC_ETH1 764 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 765 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 766 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 767 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 768 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 769 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 770 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 771 #endif /* CONFIG_UEC_ETH1 */ 772 773 #define CONFIG_UEC_ETH5 /* ETH5 */ 774 #define CONFIG_HAS_ETH1 775 776 #ifdef CONFIG_UEC_ETH5 777 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 778 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 779 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 780 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 781 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 782 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 783 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 784 #endif /* CONFIG_UEC_ETH5 */ 785 #endif /* CONFIG_TARGET_P1025RDB */ 786 787 /* 788 * Environment 789 */ 790 #ifdef CONFIG_SPIFLASH 791 #define CONFIG_ENV_IS_IN_SPI_FLASH 792 #define CONFIG_ENV_SPI_BUS 0 793 #define CONFIG_ENV_SPI_CS 0 794 #define CONFIG_ENV_SPI_MAX_HZ 10000000 795 #define CONFIG_ENV_SPI_MODE 0 796 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 797 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 798 #define CONFIG_ENV_SECT_SIZE 0x10000 799 #elif defined(CONFIG_SDCARD) 800 #define CONFIG_ENV_IS_IN_MMC 801 #define CONFIG_FSL_FIXED_MMC_LOCATION 802 #define CONFIG_ENV_SIZE 0x2000 803 #define CONFIG_SYS_MMC_ENV_DEV 0 804 #elif defined(CONFIG_NAND) 805 #ifdef CONFIG_TPL_BUILD 806 #define CONFIG_ENV_SIZE 0x2000 807 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 808 #else 809 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 810 #endif 811 #define CONFIG_ENV_IS_IN_NAND 812 #define CONFIG_ENV_OFFSET (1024 * 1024) 813 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 814 #elif defined(CONFIG_SYS_RAMBOOT) 815 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 816 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 817 #define CONFIG_ENV_SIZE 0x2000 818 #else 819 #define CONFIG_ENV_IS_IN_FLASH 820 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 821 #define CONFIG_ENV_SIZE 0x2000 822 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 823 #endif 824 825 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 826 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 827 828 /* 829 * Command line configuration. 830 */ 831 #define CONFIG_CMD_IRQ 832 #define CONFIG_CMD_DATE 833 #define CONFIG_CMD_REGINFO 834 835 /* 836 * USB 837 */ 838 #define CONFIG_HAS_FSL_DR_USB 839 840 #if defined(CONFIG_HAS_FSL_DR_USB) 841 #define CONFIG_USB_EHCI 842 843 #ifdef CONFIG_USB_EHCI 844 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 845 #define CONFIG_USB_EHCI_FSL 846 #endif 847 #endif 848 849 #if defined(CONFIG_TARGET_P1020RDB_PD) 850 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 851 #endif 852 853 #define CONFIG_MMC 854 855 #ifdef CONFIG_MMC 856 #define CONFIG_FSL_ESDHC 857 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 858 #define CONFIG_GENERIC_MMC 859 #endif 860 861 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 862 || defined(CONFIG_FSL_SATA) 863 #define CONFIG_DOS_PARTITION 864 #endif 865 866 #undef CONFIG_WATCHDOG /* watchdog disabled */ 867 868 /* 869 * Miscellaneous configurable options 870 */ 871 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 872 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 873 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 874 #if defined(CONFIG_CMD_KGDB) 875 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 876 #else 877 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 878 #endif 879 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 880 /* Print Buffer Size */ 881 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 882 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 883 884 /* 885 * For booting Linux, the board info and command line data 886 * have to be in the first 64 MB of memory, since this is 887 * the maximum mapped by the Linux kernel during initialization. 888 */ 889 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 890 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 891 892 #if defined(CONFIG_CMD_KGDB) 893 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 894 #endif 895 896 /* 897 * Environment Configuration 898 */ 899 #define CONFIG_HOSTNAME unknown 900 #define CONFIG_ROOTPATH "/opt/nfsroot" 901 #define CONFIG_BOOTFILE "uImage" 902 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 903 904 /* default location for tftp and bootm */ 905 #define CONFIG_LOADADDR 1000000 906 907 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 908 909 #define CONFIG_BAUDRATE 115200 910 911 #ifdef __SW_BOOT_NOR 912 #define __NOR_RST_CMD \ 913 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 914 i2c mw 18 3 __SW_BOOT_MASK 1; reset 915 #endif 916 #ifdef __SW_BOOT_SPI 917 #define __SPI_RST_CMD \ 918 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 919 i2c mw 18 3 __SW_BOOT_MASK 1; reset 920 #endif 921 #ifdef __SW_BOOT_SD 922 #define __SD_RST_CMD \ 923 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 924 i2c mw 18 3 __SW_BOOT_MASK 1; reset 925 #endif 926 #ifdef __SW_BOOT_NAND 927 #define __NAND_RST_CMD \ 928 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 929 i2c mw 18 3 __SW_BOOT_MASK 1; reset 930 #endif 931 #ifdef __SW_BOOT_PCIE 932 #define __PCIE_RST_CMD \ 933 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 934 i2c mw 18 3 __SW_BOOT_MASK 1; reset 935 #endif 936 937 #define CONFIG_EXTRA_ENV_SETTINGS \ 938 "netdev=eth0\0" \ 939 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 940 "loadaddr=1000000\0" \ 941 "bootfile=uImage\0" \ 942 "tftpflash=tftpboot $loadaddr $uboot; " \ 943 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 944 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 945 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 946 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 947 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 948 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 949 "consoledev=ttyS0\0" \ 950 "ramdiskaddr=2000000\0" \ 951 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 952 "fdtaddr=1e00000\0" \ 953 "bdev=sda1\0" \ 954 "jffs2nor=mtdblock3\0" \ 955 "norbootaddr=ef080000\0" \ 956 "norfdtaddr=ef040000\0" \ 957 "jffs2nand=mtdblock9\0" \ 958 "nandbootaddr=100000\0" \ 959 "nandfdtaddr=80000\0" \ 960 "ramdisk_size=120000\0" \ 961 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 962 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 963 __stringify(__NOR_RST_CMD)"\0" \ 964 __stringify(__SPI_RST_CMD)"\0" \ 965 __stringify(__SD_RST_CMD)"\0" \ 966 __stringify(__NAND_RST_CMD)"\0" \ 967 __stringify(__PCIE_RST_CMD)"\0" 968 969 #define CONFIG_NFSBOOTCOMMAND \ 970 "setenv bootargs root=/dev/nfs rw " \ 971 "nfsroot=$serverip:$rootpath " \ 972 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 973 "console=$consoledev,$baudrate $othbootargs;" \ 974 "tftp $loadaddr $bootfile;" \ 975 "tftp $fdtaddr $fdtfile;" \ 976 "bootm $loadaddr - $fdtaddr" 977 978 #define CONFIG_HDBOOT \ 979 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 980 "console=$consoledev,$baudrate $othbootargs;" \ 981 "usb start;" \ 982 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 983 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 984 "bootm $loadaddr - $fdtaddr" 985 986 #define CONFIG_USB_FAT_BOOT \ 987 "setenv bootargs root=/dev/ram rw " \ 988 "console=$consoledev,$baudrate $othbootargs " \ 989 "ramdisk_size=$ramdisk_size;" \ 990 "usb start;" \ 991 "fatload usb 0:2 $loadaddr $bootfile;" \ 992 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 993 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 994 "bootm $loadaddr $ramdiskaddr $fdtaddr" 995 996 #define CONFIG_USB_EXT2_BOOT \ 997 "setenv bootargs root=/dev/ram rw " \ 998 "console=$consoledev,$baudrate $othbootargs " \ 999 "ramdisk_size=$ramdisk_size;" \ 1000 "usb start;" \ 1001 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1002 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1003 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1004 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1005 1006 #define CONFIG_NORBOOT \ 1007 "setenv bootargs root=/dev/$jffs2nor rw " \ 1008 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1009 "bootm $norbootaddr - $norfdtaddr" 1010 1011 #define CONFIG_RAMBOOTCOMMAND \ 1012 "setenv bootargs root=/dev/ram rw " \ 1013 "console=$consoledev,$baudrate $othbootargs " \ 1014 "ramdisk_size=$ramdisk_size;" \ 1015 "tftp $ramdiskaddr $ramdiskfile;" \ 1016 "tftp $loadaddr $bootfile;" \ 1017 "tftp $fdtaddr $fdtfile;" \ 1018 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1019 1020 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1021 1022 #endif /* __CONFIG_H */ 1023