1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_36BIT 14 #define CONFIG_PHYS_64BIT 15 #endif 16 17 #if defined(CONFIG_P1020MBG) 18 #define CONFIG_BOARDNAME "P1020MBG-PC" 19 #define CONFIG_P1020 20 #define CONFIG_VSC7385_ENET 21 #define CONFIG_SLIC 22 #define __SW_BOOT_MASK 0x03 23 #define __SW_BOOT_NOR 0xe4 24 #define __SW_BOOT_SD 0x54 25 #define CONFIG_SYS_L2_SIZE (256 << 10) 26 #endif 27 28 #if defined(CONFIG_P1020UTM) 29 #define CONFIG_BOARDNAME "P1020UTM-PC" 30 #define CONFIG_P1020 31 #define __SW_BOOT_MASK 0x03 32 #define __SW_BOOT_NOR 0xe0 33 #define __SW_BOOT_SD 0x50 34 #define CONFIG_SYS_L2_SIZE (256 << 10) 35 #endif 36 37 #if defined(CONFIG_P1020RDB_PC) 38 #define CONFIG_BOARDNAME "P1020RDB-PC" 39 #define CONFIG_NAND_FSL_ELBC 40 #define CONFIG_P1020 41 #define CONFIG_SPI_FLASH 42 #define CONFIG_VSC7385_ENET 43 #define CONFIG_SLIC 44 #define __SW_BOOT_MASK 0x03 45 #define __SW_BOOT_NOR 0x5c 46 #define __SW_BOOT_SPI 0x1c 47 #define __SW_BOOT_SD 0x9c 48 #define __SW_BOOT_NAND 0xec 49 #define __SW_BOOT_PCIE 0x6c 50 #define CONFIG_SYS_L2_SIZE (256 << 10) 51 #endif 52 53 /* 54 * P1020RDB-PD board has user selectable switches for evaluating different 55 * frequency and boot options for the P1020 device. The table that 56 * follow describe the available options. The front six binary number was in 57 * accordance with SW3[1:6]. 58 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 59 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 60 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 61 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 62 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 63 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 64 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 65 */ 66 #if defined(CONFIG_P1020RDB_PD) 67 #define CONFIG_BOARDNAME "P1020RDB-PD" 68 #define CONFIG_NAND_FSL_ELBC 69 #define CONFIG_P1020 70 #define CONFIG_SPI_FLASH 71 #define CONFIG_VSC7385_ENET 72 #define CONFIG_SLIC 73 #define __SW_BOOT_MASK 0x03 74 #define __SW_BOOT_NOR 0x64 75 #define __SW_BOOT_SPI 0x34 76 #define __SW_BOOT_SD 0x24 77 #define __SW_BOOT_NAND 0x44 78 #define __SW_BOOT_PCIE 0x74 79 #define CONFIG_SYS_L2_SIZE (256 << 10) 80 #endif 81 82 #if defined(CONFIG_P1021RDB) 83 #define CONFIG_BOARDNAME "P1021RDB-PC" 84 #define CONFIG_NAND_FSL_ELBC 85 #define CONFIG_P1021 86 #define CONFIG_QE 87 #define CONFIG_SPI_FLASH 88 #define CONFIG_VSC7385_ENET 89 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 90 addresses in the LBC */ 91 #define __SW_BOOT_MASK 0x03 92 #define __SW_BOOT_NOR 0x5c 93 #define __SW_BOOT_SPI 0x1c 94 #define __SW_BOOT_SD 0x9c 95 #define __SW_BOOT_NAND 0xec 96 #define __SW_BOOT_PCIE 0x6c 97 #define CONFIG_SYS_L2_SIZE (256 << 10) 98 #endif 99 100 #if defined(CONFIG_P1024RDB) 101 #define CONFIG_BOARDNAME "P1024RDB" 102 #define CONFIG_NAND_FSL_ELBC 103 #define CONFIG_P1024 104 #define CONFIG_SLIC 105 #define CONFIG_SPI_FLASH 106 #define __SW_BOOT_MASK 0xf3 107 #define __SW_BOOT_NOR 0x00 108 #define __SW_BOOT_SPI 0x08 109 #define __SW_BOOT_SD 0x04 110 #define __SW_BOOT_NAND 0x0c 111 #define CONFIG_SYS_L2_SIZE (256 << 10) 112 #endif 113 114 #if defined(CONFIG_P1025RDB) 115 #define CONFIG_BOARDNAME "P1025RDB" 116 #define CONFIG_NAND_FSL_ELBC 117 #define CONFIG_P1025 118 #define CONFIG_QE 119 #define CONFIG_SLIC 120 #define CONFIG_SPI_FLASH 121 122 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 123 addresses in the LBC */ 124 #define __SW_BOOT_MASK 0xf3 125 #define __SW_BOOT_NOR 0x00 126 #define __SW_BOOT_SPI 0x08 127 #define __SW_BOOT_SD 0x04 128 #define __SW_BOOT_NAND 0x0c 129 #define CONFIG_SYS_L2_SIZE (256 << 10) 130 #endif 131 132 #if defined(CONFIG_P2020RDB) 133 #define CONFIG_BOARDNAME "P2020RDB-PCA" 134 #define CONFIG_NAND_FSL_ELBC 135 #define CONFIG_P2020 136 #define CONFIG_SPI_FLASH 137 #define CONFIG_VSC7385_ENET 138 #define __SW_BOOT_MASK 0x03 139 #define __SW_BOOT_NOR 0xc8 140 #define __SW_BOOT_SPI 0x28 141 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 142 #define __SW_BOOT_NAND 0xe8 143 #define __SW_BOOT_PCIE 0xa8 144 #define CONFIG_SYS_L2_SIZE (512 << 10) 145 #endif 146 147 #ifdef CONFIG_SDCARD 148 #define CONFIG_SPL 149 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 150 #define CONFIG_SPL_ENV_SUPPORT 151 #define CONFIG_SPL_SERIAL_SUPPORT 152 #define CONFIG_SPL_MMC_SUPPORT 153 #define CONFIG_SPL_MMC_MINIMAL 154 #define CONFIG_SPL_FLUSH_IMAGE 155 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 156 #define CONFIG_SPL_LIBGENERIC_SUPPORT 157 #define CONFIG_SPL_LIBCOMMON_SUPPORT 158 #define CONFIG_SPL_I2C_SUPPORT 159 #define CONFIG_FSL_LAW /* Use common FSL init code */ 160 #define CONFIG_SYS_TEXT_BASE 0x11001000 161 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 162 #define CONFIG_SPL_PAD_TO 0x18000 163 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 164 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 165 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 166 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 167 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 168 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 169 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 170 #define CONFIG_SPL_MMC_BOOT 171 #ifdef CONFIG_SPL_BUILD 172 #define CONFIG_SPL_COMMON_INIT_DDR 173 #endif 174 #endif 175 176 #ifdef CONFIG_SPIFLASH 177 #define CONFIG_RAMBOOT_SPIFLASH 178 #define CONFIG_SYS_RAMBOOT 179 #define CONFIG_SYS_EXTRA_ENV_RELOC 180 #define CONFIG_SYS_TEXT_BASE 0x11000000 181 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 182 #endif 183 184 #ifdef CONFIG_NAND 185 #define CONFIG_SPL 186 #define CONFIG_SPL_INIT_MINIMAL 187 #define CONFIG_SPL_SERIAL_SUPPORT 188 #define CONFIG_SPL_NAND_SUPPORT 189 #define CONFIG_SPL_FLUSH_IMAGE 190 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 191 192 #define CONFIG_SPL_TEXT_BASE 0xfffff000 193 #define CONFIG_SPL_MAX_SIZE 4096 194 195 #ifdef CONFIG_SYS_INIT_L2_ADDR 196 /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ 197 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 198 #define CONFIG_SPL_RELOC_TEXT_BASE \ 199 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) 200 #define CONFIG_SPL_RELOC_STACK \ 201 (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) 202 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 203 #define CONFIG_SYS_NAND_U_BOOT_START \ 204 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) 205 #else 206 #define CONFIG_SYS_TEXT_BASE 0x00201000 207 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 208 #define CONFIG_SPL_RELOC_STACK 0x00100000 209 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 210 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 211 #endif 212 213 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 214 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 215 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 216 #endif 217 218 #ifndef CONFIG_SYS_TEXT_BASE 219 #define CONFIG_SYS_TEXT_BASE 0xeff80000 220 #endif 221 222 #ifndef CONFIG_RESET_VECTOR_ADDRESS 223 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 224 #endif 225 226 #ifndef CONFIG_SYS_MONITOR_BASE 227 #ifdef CONFIG_SPL_BUILD 228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 229 #else 230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 231 #endif 232 #endif 233 234 /* High Level Configuration Options */ 235 #define CONFIG_BOOKE 236 #define CONFIG_E500 237 #define CONFIG_MPC85xx 238 239 #define CONFIG_MP 240 241 #define CONFIG_FSL_ELBC 242 #define CONFIG_PCI 243 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 244 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 245 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 246 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 247 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 248 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 249 250 #define CONFIG_FSL_LAW 251 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 252 #define CONFIG_ENV_OVERWRITE 253 254 #define CONFIG_CMD_SATA 255 #define CONFIG_SATA_SIL 256 #define CONFIG_SYS_SATA_MAX_DEVICE 2 257 #define CONFIG_LIBATA 258 #define CONFIG_LBA48 259 260 #if defined(CONFIG_P2020RDB) 261 #define CONFIG_SYS_CLK_FREQ 100000000 262 #else 263 #define CONFIG_SYS_CLK_FREQ 66666666 264 #endif 265 #define CONFIG_DDR_CLK_FREQ 66666666 266 267 #define CONFIG_HWCONFIG 268 /* 269 * These can be toggled for performance analysis, otherwise use default. 270 */ 271 #define CONFIG_L2_CACHE 272 #define CONFIG_BTB 273 274 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 275 276 #define CONFIG_ENABLE_36BIT_PHYS 277 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_ADDR_MAP 1 280 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 281 #endif 282 283 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 284 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 285 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 286 287 #define CONFIG_SYS_CCSRBAR 0xffe00000 288 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 289 290 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 291 SPL code*/ 292 #ifdef CONFIG_SPL_BUILD 293 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 294 #endif 295 296 /* DDR Setup */ 297 #define CONFIG_FSL_DDR3 298 #define CONFIG_SYS_DDR_RAW_TIMING 299 #define CONFIG_DDR_SPD 300 #define CONFIG_SYS_SPD_BUS_NUM 1 301 #define SPD_EEPROM_ADDRESS 0x52 302 #undef CONFIG_FSL_DDR_INTERACTIVE 303 304 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 305 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 306 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 307 #else 308 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 309 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 310 #endif 311 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 312 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 313 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 314 315 #define CONFIG_NUM_DDR_CONTROLLERS 1 316 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 317 318 /* Default settings for DDR3 */ 319 #ifndef CONFIG_P2020RDB 320 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 321 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 322 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 323 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 324 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 325 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 326 327 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 328 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 329 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 330 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 331 332 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 333 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 334 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 335 #define CONFIG_SYS_DDR_RCW_1 0x00000000 336 #define CONFIG_SYS_DDR_RCW_2 0x00000000 337 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 338 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 339 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 340 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 341 342 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 343 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 344 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 345 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 346 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 347 #define CONFIG_SYS_DDR_MODE_1 0x40461520 348 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 349 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 350 #endif 351 352 #undef CONFIG_CLOCKS_IN_MHZ 353 354 /* 355 * Memory map 356 * 357 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 358 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 359 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 360 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 361 * (early boot only) 362 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 363 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 364 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 365 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 366 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 367 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 368 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 369 */ 370 371 372 /* 373 * Local Bus Definitions 374 */ 375 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 376 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 377 #define CONFIG_SYS_FLASH_BASE 0xec000000 378 #elif defined(CONFIG_P1020UTM) 379 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 380 #define CONFIG_SYS_FLASH_BASE 0xee000000 381 #else 382 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 383 #define CONFIG_SYS_FLASH_BASE 0xef000000 384 #endif 385 386 387 #ifdef CONFIG_PHYS_64BIT 388 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 389 #else 390 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 391 #endif 392 393 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 394 | BR_PS_16 | BR_V) 395 396 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 397 398 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 399 #define CONFIG_SYS_FLASH_QUIET_TEST 400 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 401 402 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 403 404 #undef CONFIG_SYS_FLASH_CHECKSUM 405 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 406 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 407 408 #define CONFIG_FLASH_CFI_DRIVER 409 #define CONFIG_SYS_FLASH_CFI 410 #define CONFIG_SYS_FLASH_EMPTY_INFO 411 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 412 413 /* Nand Flash */ 414 #ifdef CONFIG_NAND_FSL_ELBC 415 #define CONFIG_SYS_NAND_BASE 0xff800000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 418 #else 419 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 420 #endif 421 422 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 423 #define CONFIG_SYS_MAX_NAND_DEVICE 1 424 #define CONFIG_MTD_NAND_VERIFY_WRITE 425 #define CONFIG_CMD_NAND 426 #if defined(CONFIG_P1020RDB_PD) 427 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 428 #else 429 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 430 #endif 431 432 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 433 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 434 | BR_PS_8 /* Port Size = 8 bit */ \ 435 | BR_MS_FCM /* MSEL = FCM */ \ 436 | BR_V) /* valid */ 437 #if defined(CONFIG_P1020RDB_PD) 438 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 439 | OR_FCM_PGS /* Large Page*/ \ 440 | OR_FCM_CSCT \ 441 | OR_FCM_CST \ 442 | OR_FCM_CHT \ 443 | OR_FCM_SCY_1 \ 444 | OR_FCM_TRLX \ 445 | OR_FCM_EHTR) 446 #else 447 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 448 | OR_FCM_CSCT \ 449 | OR_FCM_CST \ 450 | OR_FCM_CHT \ 451 | OR_FCM_SCY_1 \ 452 | OR_FCM_TRLX \ 453 | OR_FCM_EHTR) 454 #endif 455 #endif /* CONFIG_NAND_FSL_ELBC */ 456 457 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 458 459 #define CONFIG_SYS_INIT_RAM_LOCK 460 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 464 /* The assembler doesn't like typecast */ 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 466 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 467 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 468 #else 469 /* Initial L1 address */ 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 473 #endif 474 /* Size of used area in RAM */ 475 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 476 477 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 478 GENERATED_GBL_DATA_SIZE) 479 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 480 481 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 482 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 483 484 #define CONFIG_SYS_CPLD_BASE 0xffa00000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 487 #else 488 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 489 #endif 490 /* CPLD config size: 1Mb */ 491 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 492 BR_PS_8 | BR_V) 493 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 494 495 #define CONFIG_SYS_PMC_BASE 0xff980000 496 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 497 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 498 BR_PS_8 | BR_V) 499 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 500 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 501 OR_GPCM_EAD) 502 503 #ifdef CONFIG_NAND 504 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 505 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 506 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 507 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 508 #else 509 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 510 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 511 #ifdef CONFIG_NAND_FSL_ELBC 512 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 513 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 514 #endif 515 #endif 516 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 517 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 518 519 520 /* Vsc7385 switch */ 521 #ifdef CONFIG_VSC7385_ENET 522 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 523 524 #ifdef CONFIG_PHYS_64BIT 525 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 526 #else 527 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 528 #endif 529 530 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 531 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 532 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 533 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 534 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 535 536 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 537 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 538 539 /* The size of the VSC7385 firmware image */ 540 #define CONFIG_VSC7385_IMAGE_SIZE 8192 541 #endif 542 543 /* 544 * Config the L2 Cache as L2 SRAM 545 */ 546 #if defined(CONFIG_SPL_BUILD) 547 #if defined(CONFIG_SDCARD) 548 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 549 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 550 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 551 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 552 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 553 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 554 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 555 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 556 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 557 #endif 558 #endif 559 560 /* Serial Port - controlled on board with jumper J8 561 * open - index 2 562 * shorted - index 1 563 */ 564 #define CONFIG_CONS_INDEX 1 565 #undef CONFIG_SERIAL_SOFTWARE_FIFO 566 #define CONFIG_SYS_NS16550 567 #define CONFIG_SYS_NS16550_SERIAL 568 #define CONFIG_SYS_NS16550_REG_SIZE 1 569 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 570 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 571 #define CONFIG_NS16550_MIN_FUNCTIONS 572 #endif 573 574 #define CONFIG_SYS_BAUDRATE_TABLE \ 575 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 576 577 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 578 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 579 580 /* Use the HUSH parser */ 581 #define CONFIG_SYS_HUSH_PARSER 582 583 /* 584 * Pass open firmware flat tree 585 */ 586 #define CONFIG_OF_LIBFDT 587 #define CONFIG_OF_BOARD_SETUP 588 #define CONFIG_OF_STDOUT_VIA_ALIAS 589 590 /* new uImage format support */ 591 #define CONFIG_FIT 592 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 593 594 /* I2C */ 595 #define CONFIG_SYS_I2C 596 #define CONFIG_SYS_I2C_FSL 597 #define CONFIG_SYS_FSL_I2C_SPEED 400000 598 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 599 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 600 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 601 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 602 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 603 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 604 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 605 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 606 607 /* 608 * I2C2 EEPROM 609 */ 610 #undef CONFIG_ID_EEPROM 611 612 #define CONFIG_RTC_PT7C4338 613 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 614 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 615 616 /* enable read and write access to EEPROM */ 617 #define CONFIG_CMD_EEPROM 618 #define CONFIG_SYS_I2C_MULTI_EEPROMS 619 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 620 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 621 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 622 623 /* 624 * eSPI - Enhanced SPI 625 */ 626 #define CONFIG_HARD_SPI 627 #define CONFIG_FSL_ESPI 628 629 #if defined(CONFIG_SPI_FLASH) 630 #define CONFIG_SPI_FLASH_SPANSION 631 #define CONFIG_CMD_SF 632 #define CONFIG_SF_DEFAULT_SPEED 10000000 633 #define CONFIG_SF_DEFAULT_MODE 0 634 #endif 635 636 #if defined(CONFIG_PCI) 637 /* 638 * General PCI 639 * Memory space is mapped 1-1, but I/O space must start from 0. 640 */ 641 642 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 643 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 644 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 645 #ifdef CONFIG_PHYS_64BIT 646 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 647 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 648 #else 649 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 650 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 651 #endif 652 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 653 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 654 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 655 #ifdef CONFIG_PHYS_64BIT 656 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 657 #else 658 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 659 #endif 660 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 661 662 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 663 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 664 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 665 #ifdef CONFIG_PHYS_64BIT 666 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 667 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 668 #else 669 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 670 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 671 #endif 672 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 673 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 674 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 675 #ifdef CONFIG_PHYS_64BIT 676 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 677 #else 678 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 679 #endif 680 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 681 682 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 683 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ 684 #define CONFIG_CMD_PCI 685 #define CONFIG_CMD_NET 686 687 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 688 #define CONFIG_DOS_PARTITION 689 #endif /* CONFIG_PCI */ 690 691 #if defined(CONFIG_TSEC_ENET) 692 #define CONFIG_MII /* MII PHY management */ 693 #define CONFIG_TSEC1 694 #define CONFIG_TSEC1_NAME "eTSEC1" 695 #define CONFIG_TSEC2 696 #define CONFIG_TSEC2_NAME "eTSEC2" 697 #define CONFIG_TSEC3 698 #define CONFIG_TSEC3_NAME "eTSEC3" 699 700 #define TSEC1_PHY_ADDR 2 701 #define TSEC2_PHY_ADDR 0 702 #define TSEC3_PHY_ADDR 1 703 704 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 705 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 706 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 707 708 #define TSEC1_PHYIDX 0 709 #define TSEC2_PHYIDX 0 710 #define TSEC3_PHYIDX 0 711 712 #define CONFIG_ETHPRIME "eTSEC1" 713 714 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 715 716 #define CONFIG_HAS_ETH0 717 #define CONFIG_HAS_ETH1 718 #define CONFIG_HAS_ETH2 719 #endif /* CONFIG_TSEC_ENET */ 720 721 #ifdef CONFIG_QE 722 /* QE microcode/firmware address */ 723 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 724 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000 725 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 726 #endif /* CONFIG_QE */ 727 728 #ifdef CONFIG_P1025RDB 729 /* 730 * QE UEC ethernet configuration 731 */ 732 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 733 734 #undef CONFIG_UEC_ETH 735 #define CONFIG_PHY_MODE_NEED_CHANGE 736 737 #define CONFIG_UEC_ETH1 /* ETH1 */ 738 #define CONFIG_HAS_ETH0 739 740 #ifdef CONFIG_UEC_ETH1 741 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 742 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 743 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 744 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 745 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 746 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 747 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 748 #endif /* CONFIG_UEC_ETH1 */ 749 750 #define CONFIG_UEC_ETH5 /* ETH5 */ 751 #define CONFIG_HAS_ETH1 752 753 #ifdef CONFIG_UEC_ETH5 754 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 755 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 756 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 757 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 758 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 759 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 760 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 761 #endif /* CONFIG_UEC_ETH5 */ 762 #endif /* CONFIG_P1025RDB */ 763 764 /* 765 * Environment 766 */ 767 #ifdef CONFIG_RAMBOOT_SPIFLASH 768 #define CONFIG_ENV_IS_IN_SPI_FLASH 769 #define CONFIG_ENV_SPI_BUS 0 770 #define CONFIG_ENV_SPI_CS 0 771 #define CONFIG_ENV_SPI_MAX_HZ 10000000 772 #define CONFIG_ENV_SPI_MODE 0 773 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 774 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 775 #define CONFIG_ENV_SECT_SIZE 0x10000 776 #elif defined(CONFIG_SDCARD) 777 #define CONFIG_ENV_IS_IN_MMC 778 #define CONFIG_FSL_FIXED_MMC_LOCATION 779 #define CONFIG_ENV_SIZE 0x2000 780 #define CONFIG_SYS_MMC_ENV_DEV 0 781 #elif defined(CONFIG_NAND) 782 #define CONFIG_ENV_IS_IN_NAND 783 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 784 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 785 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 786 #elif defined(CONFIG_SYS_RAMBOOT) 787 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 788 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 789 #define CONFIG_ENV_SIZE 0x2000 790 #else 791 #define CONFIG_ENV_IS_IN_FLASH 792 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 793 #define CONFIG_ENV_ADDR 0xfff80000 794 #else 795 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 796 #endif 797 #define CONFIG_ENV_SIZE 0x2000 798 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 799 #endif 800 801 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 802 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 803 804 /* 805 * Command line configuration. 806 */ 807 #include <config_cmd_default.h> 808 809 #define CONFIG_CMD_IRQ 810 #define CONFIG_CMD_PING 811 #define CONFIG_CMD_I2C 812 #define CONFIG_CMD_MII 813 #define CONFIG_CMD_DATE 814 #define CONFIG_CMD_ELF 815 #define CONFIG_CMD_SETEXPR 816 #define CONFIG_CMD_REGINFO 817 818 /* 819 * USB 820 */ 821 #define CONFIG_HAS_FSL_DR_USB 822 823 #if defined(CONFIG_HAS_FSL_DR_USB) 824 #define CONFIG_USB_EHCI 825 826 #ifdef CONFIG_USB_EHCI 827 #define CONFIG_CMD_USB 828 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 829 #define CONFIG_USB_EHCI_FSL 830 #define CONFIG_USB_STORAGE 831 #endif 832 #endif 833 834 #define CONFIG_MMC 835 836 #ifdef CONFIG_MMC 837 #define CONFIG_FSL_ESDHC 838 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 839 #define CONFIG_CMD_MMC 840 #define CONFIG_GENERIC_MMC 841 #endif 842 843 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 844 || defined(CONFIG_FSL_SATA) 845 #define CONFIG_CMD_EXT2 846 #define CONFIG_CMD_FAT 847 #define CONFIG_DOS_PARTITION 848 #endif 849 850 #undef CONFIG_WATCHDOG /* watchdog disabled */ 851 852 /* 853 * Miscellaneous configurable options 854 */ 855 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 856 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 857 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 858 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 859 #if defined(CONFIG_CMD_KGDB) 860 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 861 #else 862 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 863 #endif 864 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 865 /* Print Buffer Size */ 866 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 867 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 868 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 869 870 /* 871 * For booting Linux, the board info and command line data 872 * have to be in the first 64 MB of memory, since this is 873 * the maximum mapped by the Linux kernel during initialization. 874 */ 875 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 876 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 877 878 #if defined(CONFIG_CMD_KGDB) 879 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 880 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 881 #endif 882 883 /* 884 * Environment Configuration 885 */ 886 #define CONFIG_HOSTNAME unknown 887 #define CONFIG_ROOTPATH "/opt/nfsroot" 888 #define CONFIG_BOOTFILE "uImage" 889 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 890 891 /* default location for tftp and bootm */ 892 #define CONFIG_LOADADDR 1000000 893 894 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 895 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 896 897 #define CONFIG_BAUDRATE 115200 898 899 #ifdef __SW_BOOT_NOR 900 #define __NOR_RST_CMD \ 901 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 902 i2c mw 18 3 __SW_BOOT_MASK 1; reset 903 #endif 904 #ifdef __SW_BOOT_SPI 905 #define __SPI_RST_CMD \ 906 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 907 i2c mw 18 3 __SW_BOOT_MASK 1; reset 908 #endif 909 #ifdef __SW_BOOT_SD 910 #define __SD_RST_CMD \ 911 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 912 i2c mw 18 3 __SW_BOOT_MASK 1; reset 913 #endif 914 #ifdef __SW_BOOT_NAND 915 #define __NAND_RST_CMD \ 916 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 917 i2c mw 18 3 __SW_BOOT_MASK 1; reset 918 #endif 919 #ifdef __SW_BOOT_PCIE 920 #define __PCIE_RST_CMD \ 921 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 922 i2c mw 18 3 __SW_BOOT_MASK 1; reset 923 #endif 924 925 #define CONFIG_EXTRA_ENV_SETTINGS \ 926 "netdev=eth0\0" \ 927 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 928 "loadaddr=1000000\0" \ 929 "bootfile=uImage\0" \ 930 "tftpflash=tftpboot $loadaddr $uboot; " \ 931 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 932 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 933 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 934 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 935 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 936 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 937 "consoledev=ttyS0\0" \ 938 "ramdiskaddr=2000000\0" \ 939 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 940 "fdtaddr=c00000\0" \ 941 "bdev=sda1\0" \ 942 "jffs2nor=mtdblock3\0" \ 943 "norbootaddr=ef080000\0" \ 944 "norfdtaddr=ef040000\0" \ 945 "jffs2nand=mtdblock9\0" \ 946 "nandbootaddr=100000\0" \ 947 "nandfdtaddr=80000\0" \ 948 "ramdisk_size=120000\0" \ 949 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 950 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 951 __stringify(__NOR_RST_CMD)"\0" \ 952 __stringify(__SPI_RST_CMD)"\0" \ 953 __stringify(__SD_RST_CMD)"\0" \ 954 __stringify(__NAND_RST_CMD)"\0" \ 955 __stringify(__PCIE_RST_CMD)"\0" 956 957 #define CONFIG_NFSBOOTCOMMAND \ 958 "setenv bootargs root=/dev/nfs rw " \ 959 "nfsroot=$serverip:$rootpath " \ 960 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 961 "console=$consoledev,$baudrate $othbootargs;" \ 962 "tftp $loadaddr $bootfile;" \ 963 "tftp $fdtaddr $fdtfile;" \ 964 "bootm $loadaddr - $fdtaddr" 965 966 #define CONFIG_HDBOOT \ 967 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 968 "console=$consoledev,$baudrate $othbootargs;" \ 969 "usb start;" \ 970 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 971 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 972 "bootm $loadaddr - $fdtaddr" 973 974 #define CONFIG_USB_FAT_BOOT \ 975 "setenv bootargs root=/dev/ram rw " \ 976 "console=$consoledev,$baudrate $othbootargs " \ 977 "ramdisk_size=$ramdisk_size;" \ 978 "usb start;" \ 979 "fatload usb 0:2 $loadaddr $bootfile;" \ 980 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 981 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 982 "bootm $loadaddr $ramdiskaddr $fdtaddr" 983 984 #define CONFIG_USB_EXT2_BOOT \ 985 "setenv bootargs root=/dev/ram rw " \ 986 "console=$consoledev,$baudrate $othbootargs " \ 987 "ramdisk_size=$ramdisk_size;" \ 988 "usb start;" \ 989 "ext2load usb 0:4 $loadaddr $bootfile;" \ 990 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 991 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 992 "bootm $loadaddr $ramdiskaddr $fdtaddr" 993 994 #define CONFIG_NORBOOT \ 995 "setenv bootargs root=/dev/$jffs2nor rw " \ 996 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 997 "bootm $norbootaddr - $norfdtaddr" 998 999 #define CONFIG_RAMBOOTCOMMAND \ 1000 "setenv bootargs root=/dev/ram rw " \ 1001 "console=$consoledev,$baudrate $othbootargs " \ 1002 "ramdisk_size=$ramdisk_size;" \ 1003 "tftp $ramdiskaddr $ramdiskfile;" \ 1004 "tftp $loadaddr $bootfile;" \ 1005 "tftp $fdtaddr $fdtfile;" \ 1006 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1007 1008 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1009 1010 #endif /* __CONFIG_H */ 1011