1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014 Bachmann electronic GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include "mx6_common.h" 12 13 /* Size of malloc() pool */ 14 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 15 16 #define CONFIG_BOARD_EARLY_INIT_F 17 #define CONFIG_MISC_INIT_R 18 19 /* FUSE Configs */ 20 #define CONFIG_CMD_FUSE 21 #define CONFIG_MXC_OCOTP 22 23 /* UART Configs */ 24 #define CONFIG_MXC_UART 25 #define CONFIG_MXC_UART_BASE UART1_BASE 26 27 /* SF Configs */ 28 #define CONFIG_CMD_SF 29 #define CONFIG_SPI 30 #define CONFIG_SPI_FLASH 31 #define CONFIG_SPI_FLASH_STMICRO 32 #define CONFIG_SPI_FLASH_WINBOND 33 #define CONFIG_SPI_FLASH_MACRONIX 34 #define CONFIG_SPI_FLASH_SST 35 #define CONFIG_MXC_SPI 36 #define CONFIG_SF_DEFAULT_BUS 2 37 #define CONFIG_SF_DEFAULT_CS 0 38 #define CONFIG_SF_DEFAULT_SPEED 25000000 39 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 40 41 /* IO expander */ 42 #define CONFIG_PCA953X 43 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 44 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 45 #define CONFIG_CMD_PCA953X 46 #define CONFIG_CMD_PCA953X_INFO 47 48 /* I2C Configs */ 49 #define CONFIG_CMD_I2C 50 #define CONFIG_SYS_I2C 51 #define CONFIG_SYS_I2C_MXC 52 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 53 #define CONFIG_SYS_I2C_SPEED 100000 54 55 /* OCOTP Configs */ 56 #define CONFIG_CMD_IMXOTP 57 #define CONFIG_IMX_OTP 58 #define IMX_OTP_BASE OCOTP_BASE_ADDR 59 #define IMX_OTP_ADDR_MAX 0x7F 60 #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 61 #define IMX_OTPWRITE_ENABLED 62 63 /* MMC Configs */ 64 #define CONFIG_FSL_ESDHC 65 #define CONFIG_FSL_USDHC 66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 67 #define CONFIG_SYS_FSL_USDHC_NUM 2 68 69 #define CONFIG_MMC 70 #define CONFIG_CMD_MMC 71 #define CONFIG_GENERIC_MMC 72 #define CONFIG_BOUNCE_BUFFER 73 74 /* USB Configs */ 75 #define CONFIG_CMD_USB 76 #define CONFIG_USB_STORAGE 77 #define CONFIG_USB_EHCI 78 #define CONFIG_USB_EHCI_MX6 79 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 80 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 81 82 #ifdef CONFIG_MX6Q 83 #define CONFIG_CMD_SATA 84 #endif 85 86 /* 87 * SATA Configs 88 */ 89 #ifdef CONFIG_CMD_SATA 90 #define CONFIG_DWC_AHSATA 91 #define CONFIG_SYS_SATA_MAX_DEVICE 1 92 #define CONFIG_DWC_AHSATA_PORT_ID 0 93 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 94 #define CONFIG_LBA48 95 #define CONFIG_LIBATA 96 #endif 97 98 99 /* SPL */ 100 #ifdef CONFIG_SPL 101 #include "imx6_spl.h" 102 #define CONFIG_SPL_SPI_SUPPORT 103 #define CONFIG_SPL_LIBCOMMON_SUPPORT 104 #define CONFIG_SPL_SPI_FLASH_SUPPORT 105 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 106 #define CONFIG_SPL_SPI_LOAD 107 #endif 108 109 #define CONFIG_CMD_PING 110 #define CONFIG_CMD_DHCP 111 #define CONFIG_CMD_MII 112 #define CONFIG_CMD_NET 113 #define CONFIG_FEC_MXC 114 #define CONFIG_MII 115 #define IMX_FEC_BASE ENET_BASE_ADDR 116 #define CONFIG_FEC_XCV_TYPE MII100 117 #define CONFIG_ETHPRIME "FEC" 118 #define CONFIG_FEC_MXC_PHYADDR 0x5 119 #define CONFIG_PHYLIB 120 #define CONFIG_PHY_SMSC 121 122 #ifndef CONFIG_SPL 123 #define CONFIG_CMD_EEPROM 124 #define CONFIG_ENV_EEPROM_IS_ON_I2C 125 #define CONFIG_SYS_I2C_EEPROM_BUS 1 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 128 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 129 #define CONFIG_SYS_I2C_MULTI_EEPROMS 130 #endif 131 132 /* Miscellaneous commands */ 133 #define CONFIG_CMD_BMODE 134 #define CONFIG_CMD_SETEXPR 135 136 /* allow to overwrite serial and ethaddr */ 137 #define CONFIG_ENV_OVERWRITE 138 #define CONFIG_CONS_INDEX 1 139 #define CONFIG_BAUDRATE 115200 140 141 /* Command definition */ 142 143 #define CONFIG_BOOTDELAY 2 144 145 #define CONFIG_PREBOOT "" 146 147 #define CONFIG_LOADADDR 0x12000000 148 #define CONFIG_SYS_TEXT_BASE 0x17800000 149 150 /* Miscellaneous configurable options */ 151 #define CONFIG_SYS_LONGHELP 152 #define CONFIG_SYS_HUSH_PARSER 153 #define CONFIG_SYS_CBSIZE 1024 154 155 /* Print Buffer Size */ 156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 157 #define CONFIG_SYS_MAXARGS 16 158 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 159 160 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 161 162 #define CONFIG_CMDLINE_EDITING 163 164 /* Physical Memory Map */ 165 #define CONFIG_NR_DRAM_BANKS 1 166 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 167 168 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 169 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 170 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 171 172 #define CONFIG_SYS_INIT_SP_OFFSET \ 173 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 174 #define CONFIG_SYS_INIT_SP_ADDR \ 175 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 176 177 /* Environment organization */ 178 #define CONFIG_ENV_IS_IN_SPI_FLASH 179 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ 180 #define CONFIG_ENV_OFFSET (1024 * 1024) 181 /* M25P16 has an erase size of 64 KiB */ 182 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 183 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 184 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 185 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 186 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 187 188 #define CONFIG_OF_LIBFDT 189 #define CONFIG_CMD_BOOTZ 190 191 #ifndef CONFIG_SYS_DCACHE_OFF 192 #define CONFIG_CMD_CACHE 193 #endif 194 195 #define CONFIG_CMD_BOOTZ 196 #define CONFIG_SUPPORT_RAW_INITRD 197 198 /* FS Configs */ 199 #define CONFIG_CMD_EXT3 200 #define CONFIG_CMD_EXT4 201 #define CONFIG_DOS_PARTITION 202 #define CONFIG_CMD_FS_GENERIC 203 #define CONFIG_LIB_UUID 204 #define CONFIG_CMD_FS_UUID 205 206 #define CONFIG_BOOTP_SERVERIP 207 #define CONFIG_BOOTP_BOOTFILE 208 209 #endif /* __CONFIG_H */ 210