1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 #undef CONFIG_USE_SPIFLASH 19 #undef CONFIG_SYS_USE_NOR 20 #define CONFIG_USE_NAND 21 22 /* 23 * SoC Configuration 24 */ 25 #define CONFIG_MACH_OMAPL138_LCDK 26 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 27 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 28 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 29 #define CONFIG_SYS_OSCIN_FREQ 24000000 30 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 31 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 32 #define CONFIG_SYS_HZ 1000 33 #define CONFIG_SKIP_LOWLEVEL_INIT 34 #define CONFIG_SYS_TEXT_BASE 0xc1080000 35 36 /* 37 * Memory Info 38 */ 39 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 40 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 41 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 42 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 43 44 /* memtest start addr */ 45 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 46 47 /* memtest will be run on 16MB */ 48 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 49 50 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 51 #define CONFIG_STACKSIZE (256*1024) /* regular stack */ 52 53 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 54 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 55 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 56 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 57 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 58 DAVINCI_SYSCFG_SUSPSRC_I2C) 59 60 /* 61 * PLL configuration 62 */ 63 #define CONFIG_SYS_DV_CLKMODE 0 64 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 65 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 66 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 67 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 68 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 69 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 70 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 71 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 72 73 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 74 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 75 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 76 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 77 78 #define CONFIG_SYS_DA850_PLL0_PLLM 24 79 #define CONFIG_SYS_DA850_PLL1_PLLM 21 80 81 /* 82 * DDR2 memory configuration 83 */ 84 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 85 DV_DDR_PHY_EXT_STRBEN | \ 86 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 87 88 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 89 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 90 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 91 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 92 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 93 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 94 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 95 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 96 97 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 98 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 99 100 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 101 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 102 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 103 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 104 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 105 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 106 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 107 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 108 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 109 110 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 111 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 112 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 113 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 114 (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 115 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 116 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 117 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 118 119 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 120 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 121 122 /* 123 * Serial Driver info 124 */ 125 #define CONFIG_SYS_NS16550_SERIAL 126 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 127 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 128 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 129 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 130 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 131 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 132 133 #define CONFIG_SPI 134 #define CONFIG_DAVINCI_SPI 135 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 136 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 137 #define CONFIG_SF_DEFAULT_SPEED 30000000 138 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 139 140 #ifdef CONFIG_USE_SPIFLASH 141 #define CONFIG_SPL_SPI_LOAD 142 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 143 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 144 #endif 145 146 /* 147 * I2C Configuration 148 */ 149 #define CONFIG_SYS_I2C 150 #define CONFIG_SYS_I2C_DAVINCI 151 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 152 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 153 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 154 155 /* 156 * Flash & Environment 157 */ 158 #ifdef CONFIG_USE_NAND 159 #undef CONFIG_ENV_IS_IN_FLASH 160 #define CONFIG_NAND_DAVINCI 161 #define CONFIG_SYS_NO_FLASH 162 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 163 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 164 #define CONFIG_ENV_SIZE (128 << 9) 165 #define CONFIG_SYS_NAND_USE_FLASH_BBT 166 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 167 #define CONFIG_SYS_NAND_PAGE_2K 168 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 169 #define CONFIG_SYS_NAND_CS 3 170 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 171 #define CONFIG_SYS_CLE_MASK 0x10 172 #define CONFIG_SYS_ALE_MASK 0x8 173 #undef CONFIG_SYS_NAND_HW_ECC 174 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 175 #define NAND_MAX_CHIPS 1 176 #endif 177 178 #ifdef CONFIG_SYS_USE_NOR 179 #define CONFIG_ENV_IS_IN_FLASH 180 #undef CONFIG_SYS_NO_FLASH 181 #define CONFIG_FLASH_CFI_DRIVER 182 #define CONFIG_SYS_FLASH_CFI 183 #define CONFIG_SYS_FLASH_PROTECTION 184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 185 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 186 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 187 #define CONFIG_ENV_SIZE (128 << 10) 188 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 189 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 190 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 191 + 3) 192 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 193 #endif 194 195 #ifdef CONFIG_USE_SPIFLASH 196 #undef CONFIG_ENV_IS_IN_FLASH 197 #undef CONFIG_ENV_IS_IN_NAND 198 #define CONFIG_ENV_IS_IN_SPI_FLASH 199 #define CONFIG_ENV_SIZE (64 << 10) 200 #define CONFIG_ENV_OFFSET (256 << 10) 201 #define CONFIG_ENV_SECT_SIZE (64 << 10) 202 #define CONFIG_SYS_NO_FLASH 203 #endif 204 205 /* 206 * Network & Ethernet Configuration 207 */ 208 #ifdef CONFIG_DRIVER_TI_EMAC 209 #define CONFIG_EMAC_MDIO_PHY_NUM 7 210 #define CONFIG_MII 211 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII 212 #define CONFIG_BOOTP_DEFAULT 213 #define CONFIG_BOOTP_DNS 214 #define CONFIG_BOOTP_DNS2 215 #define CONFIG_BOOTP_SEND_HOSTNAME 216 #define CONFIG_NET_RETRY_COUNT 10 217 #endif 218 219 /* 220 * U-Boot general configuration 221 */ 222 #define CONFIG_MISC_INIT_R 223 #define CONFIG_BOARD_EARLY_INIT_F 224 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 225 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 227 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 228 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 229 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 230 #define CONFIG_AUTO_COMPLETE 231 #define CONFIG_CMDLINE_EDITING 232 #define CONFIG_SYS_LONGHELP 233 #define CONFIG_CRC32_VERIFY 234 #define CONFIG_MX_CYCLIC 235 236 /* 237 * Linux Information 238 */ 239 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 240 #define CONFIG_CMDLINE_TAG 241 #define CONFIG_REVISION_TAG 242 #define CONFIG_SETUP_MEMORY_TAGS 243 #define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" 244 #define CONFIG_BOOTCOMMAND "if mmc rescan; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" 245 246 /* 247 * U-Boot commands 248 */ 249 #define CONFIG_CMD_ENV 250 #define CONFIG_CMD_DIAG 251 #define CONFIG_CMD_SAVES 252 #ifdef CONFIG_CMD_BDI 253 #define CONFIG_CLOCKS 254 #endif 255 256 #ifndef CONFIG_DRIVER_TI_EMAC 257 #endif 258 259 #ifdef CONFIG_USE_NAND 260 #define CONFIG_CMD_NAND 261 262 #define CONFIG_CMD_MTDPARTS 263 #define CONFIG_MTD_DEVICE 264 #define CONFIG_MTD_PARTITIONS 265 #define CONFIG_LZO 266 #define CONFIG_RBTREE 267 #define CONFIG_CMD_UBIFS 268 #endif 269 270 #ifdef CONFIG_USE_SPIFLASH 271 #endif 272 273 #if !defined(CONFIG_USE_NAND) && \ 274 !defined(CONFIG_SYS_USE_NOR) && \ 275 !defined(CONFIG_USE_SPIFLASH) 276 #define CONFIG_ENV_IS_NOWHERE 277 #define CONFIG_SYS_NO_FLASH 278 #define CONFIG_ENV_SIZE (16 << 10) 279 #undef CONFIG_CMD_ENV 280 #endif 281 282 /* SD/MMC */ 283 #define CONFIG_MMC 284 #define CONFIG_GENERIC_MMC 285 #define CONFIG_DAVINCI_MMC 286 287 #ifdef CONFIG_MMC 288 #define CONFIG_DOS_PARTITION 289 #undef CONFIG_ENV_IS_IN_MMC 290 #endif 291 292 #ifdef CONFIG_ENV_IS_IN_MMC 293 #undef CONFIG_ENV_SIZE 294 #undef CONFIG_ENV_OFFSET 295 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 296 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ 297 #undef CONFIG_ENV_IS_IN_FLASH 298 #undef CONFIG_ENV_IS_IN_NAND 299 #undef CONFIG_ENV_IS_IN_SPI_FLASH 300 #endif 301 302 #ifndef CONFIG_DIRECT_NOR_BOOT 303 /* defines for SPL */ 304 #define CONFIG_SPL_FRAMEWORK 305 #define CONFIG_SPL_BOARD_INIT 306 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 307 CONFIG_SYS_MALLOC_LEN) 308 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 309 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" 310 #define CONFIG_SPL_STACK 0x8001ff00 311 #define CONFIG_SPL_TEXT_BASE 0x80000000 312 #define CONFIG_SPL_MAX_FOOTPRINT 32768 313 #define CONFIG_SPL_PAD_TO 32768 314 #endif 315 316 /* additions for new relocation code, must added to all boards */ 317 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 318 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 319 GENERATED_GBL_DATA_SIZE) 320 #endif /* __CONFIG_H */ 321