1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * Nishanth Menon <nm@ti.com> 7 * 8 * Configuration settings for the TI OMAP3430 Zoom MDK board. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 21 #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ 22 #define CONFIG_OMAP_COMMON 23 #define CONFIG_SYS_GENERIC_BOARD 24 25 #define CONFIG_SDRC /* The chip has SDRC controller */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap3.h> 29 30 /* 31 * Display CPU and Board information 32 */ 33 #define CONFIG_DISPLAY_CPUINFO 1 34 #define CONFIG_DISPLAY_BOARDINFO 1 35 36 /* Clock Defines */ 37 #define V_OSCK 26000000 /* Clock output from T2 */ 38 #define V_SCLK (V_OSCK >> 1) 39 40 #define CONFIG_MISC_INIT_R 41 42 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 43 #define CONFIG_SETUP_MEMORY_TAGS 1 44 #define CONFIG_INITRD_TAG 1 45 #define CONFIG_REVISION_TAG 1 46 47 #define CONFIG_OF_LIBFDT 1 48 49 /* 50 * Size of malloc() pool 51 */ 52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 53 /* Sector */ 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 55 56 /* 57 * Hardware drivers 58 */ 59 60 /* 61 * NS16550 Configuration 62 */ 63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 64 65 #define CONFIG_SYS_NS16550 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SERIAL3 3 /* UART3 */ 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 115200} 82 #define CONFIG_GENERIC_MMC 1 83 #define CONFIG_MMC 1 84 #define CONFIG_OMAP_HSMMC 1 85 #define CONFIG_DOS_PARTITION 1 86 87 /* USB */ 88 #define CONFIG_MUSB_UDC 1 89 #define CONFIG_USB_OMAP3 1 90 #define CONFIG_TWL4030_USB 1 91 92 /* USB device configuration */ 93 #define CONFIG_USB_DEVICE 1 94 #define CONFIG_USB_TTY 1 95 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 96 /* Change these to suit your needs */ 97 #define CONFIG_USBD_VENDORID 0x0451 98 #define CONFIG_USBD_PRODUCTID 0x5678 99 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 100 #define CONFIG_USBD_PRODUCT_NAME "Zoom1" 101 102 /* commands to include */ 103 #include <config_cmd_default.h> 104 105 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 106 #define CONFIG_CMD_FAT /* FAT support */ 107 #define CONFIG_CMD_FS_GENERIC /* Generic FS support */ 108 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 109 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 110 #define MTDIDS_DEFAULT "nand0=nand" 111 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 112 "1920k(u-boot),128k(u-boot-env),"\ 113 "4m(kernel),-(fs)" 114 115 #define CONFIG_CMD_I2C /* I2C serial bus support */ 116 #define CONFIG_CMD_MMC /* MMC support */ 117 #define CONFIG_CMD_NAND /* NAND support */ 118 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ 119 120 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 121 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 122 #undef CONFIG_CMD_IMI /* iminfo */ 123 #undef CONFIG_CMD_IMLS /* List all found images */ 124 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 125 #define CONFIG_CMD_NFS /* NFS support */ 126 #define CONFIG_CMD_PING 127 #define CONFIG_CMD_DHCP 128 129 #define CONFIG_SYS_NO_FLASH 130 #define CONFIG_SYS_I2C 131 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 132 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 133 #define CONFIG_SYS_I2C_OMAP34XX 134 135 /* 136 * TWL4030 137 */ 138 #define CONFIG_TWL4030_POWER 1 139 #define CONFIG_TWL4030_LED 1 140 141 /* 142 * Board NAND Info. 143 */ 144 #define CONFIG_NAND_OMAP_GPMC 145 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 146 /* to access nand */ 147 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 148 /* to access nand at */ 149 /* CS0 */ 150 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 151 /* devices */ 152 153 /* Environment information */ 154 #define CONFIG_BOOTDELAY 10 155 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "loadaddr=0x82000000\0" \ 158 "bootfile=uImage\0" \ 159 "bootdir=/\0" \ 160 "bootpart=0:1\0" \ 161 "usbtty=cdc_acm\0" \ 162 "console=ttyS2,115200n8\0" \ 163 "mmcdev=0\0" \ 164 "videomode=1024x768@60,vxres=1024,vyres=768\0" \ 165 "videospec=omapfb:vram:2M,vram:4M\0" \ 166 "mmcargs=setenv bootargs console=${console} " \ 167 "video=${videospec},mode:${videomode} " \ 168 "root=/dev/mmcblk0p2 rw " \ 169 "rootfstype=ext3 rootwait\0" \ 170 "nandargs=setenv bootargs console=${console} " \ 171 "video=${videospec},mode:${videomode} " \ 172 "root=/dev/mtdblock4 rw " \ 173 "rootfstype=jffs2\0" \ 174 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 175 "bootscript=echo Running bootscript from mmc ...; " \ 176 "source ${loadaddr}\0" \ 177 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ 178 "mmcboot=echo Booting from mmc ...; " \ 179 "run mmcargs; " \ 180 "bootm ${loadaddr}\0" \ 181 "nandboot=echo Booting from nand ...; " \ 182 "run nandargs; " \ 183 "nand read ${loadaddr} 280000 400000; " \ 184 "bootm ${loadaddr}\0" \ 185 186 #define CONFIG_BOOTCOMMAND \ 187 "mmc dev ${mmcdev}; if mmc rescan; then " \ 188 "if run loadbootscript; then " \ 189 "run bootscript; " \ 190 "else " \ 191 "if run loadimage; then " \ 192 "run mmcboot; " \ 193 "else run nandboot; " \ 194 "fi; " \ 195 "fi; " \ 196 "else run nandboot; fi" 197 198 #define CONFIG_AUTO_COMPLETE 1 199 /* 200 * Miscellaneous configurable options 201 */ 202 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 203 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 204 #define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # " 205 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 206 /* Print Buffer Size */ 207 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 208 sizeof(CONFIG_SYS_PROMPT) + 16) 209 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 210 /* Boot Argument Buffer Size */ 211 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 212 213 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 214 /* works on */ 215 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 216 0x01F00000) /* 31MB */ 217 218 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 219 /* load address */ 220 221 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 222 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 223 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 224 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 225 CONFIG_SYS_INIT_RAM_SIZE - \ 226 GENERATED_GBL_DATA_SIZE) 227 /* 228 * OMAP3 has 12 GP timers, they can be driven by the system clock 229 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 230 * This rate is divided by a local divisor. 231 */ 232 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 233 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 234 235 /*----------------------------------------------------------------------- 236 * Physical Memory Map 237 */ 238 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 239 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 240 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 241 242 /*----------------------------------------------------------------------- 243 * FLASH and environment organization 244 */ 245 246 /* **** PISMO SUPPORT *** */ 247 248 /* Configure the PISMO */ 249 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 250 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 251 252 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 253 254 #if defined(CONFIG_CMD_NAND) 255 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 256 #endif 257 258 /* Monitor at start of flash */ 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 260 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 261 262 #define CONFIG_ENV_IS_IN_NAND 1 263 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 264 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 265 266 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 267 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 268 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 269 270 #define CONFIG_SYS_CACHELINE_SIZE 64 271 272 #ifdef CONFIG_CMD_NET 273 /* Ethernet (LAN9211 from SMSC9118 family) */ 274 #define CONFIG_SMC911X 275 #define CONFIG_SMC911X_32_BIT 276 #define CONFIG_SMC911X_BASE DEBUG_BASE 277 278 #endif 279 280 #endif /* __CONFIG_H */ 281