1 /* 2 * (C) Copyright 2008 3 * Grazvydas Ignotas <notasas@gmail.com> 4 * 5 * Configuration settings for the OMAP3 Pandora. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 #include <asm/sizes.h> 26 27 /* 28 * High Level Configuration Options 29 */ 30 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 31 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 33 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 34 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap3.h> 38 39 /* 40 * Display CPU and Board information 41 */ 42 #define CONFIG_DISPLAY_CPUINFO 1 43 #define CONFIG_DISPLAY_BOARDINFO 1 44 45 /* Clock Defines */ 46 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_SCLK (V_OSCK >> 1) 48 49 #undef CONFIG_USE_IRQ /* no support for IRQs */ 50 #define CONFIG_MISC_INIT_R 51 52 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 53 #define CONFIG_SETUP_MEMORY_TAGS 1 54 #define CONFIG_INITRD_TAG 1 55 #define CONFIG_REVISION_TAG 1 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 63 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 64 /* initial data */ 65 66 /* 67 * Hardware drivers 68 */ 69 70 /* 71 * NS16550 Configuration 72 */ 73 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 74 75 #define CONFIG_SYS_NS16550 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 78 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 79 80 /* 81 * select serial console configuration 82 */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 86 87 /* allow to overwrite serial and ethaddr */ 88 #define CONFIG_ENV_OVERWRITE 89 #define CONFIG_BAUDRATE 115200 90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 91 115200} 92 #define CONFIG_MMC 1 93 #define CONFIG_OMAP3_MMC 1 94 #define CONFIG_DOS_PARTITION 1 95 96 /* commands to include */ 97 #include <config_cmd_default.h> 98 99 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 100 #define CONFIG_CMD_FAT /* FAT support */ 101 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 102 103 #define CONFIG_CMD_I2C /* I2C serial bus support */ 104 #define CONFIG_CMD_MMC /* MMC support */ 105 #define CONFIG_CMD_NAND /* NAND support */ 106 107 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 108 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 109 #undef CONFIG_CMD_IMI /* iminfo */ 110 #undef CONFIG_CMD_IMLS /* List all found images */ 111 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 112 #undef CONFIG_CMD_NFS /* NFS support */ 113 114 #define CONFIG_SYS_NO_FLASH 115 #define CONFIG_SYS_I2C_SPEED 100000 116 #define CONFIG_SYS_I2C_SLAVE 1 117 #define CONFIG_SYS_I2C_BUS 0 118 #define CONFIG_SYS_I2C_BUS_SELECT 1 119 #define CONFIG_DRIVER_OMAP34XX_I2C 1 120 121 /* 122 * Board NAND Info. 123 */ 124 #define CONFIG_NAND_OMAP_GPMC 125 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 126 /* to access nand */ 127 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 128 /* to access nand */ 129 /* at CS0 */ 130 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 131 132 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 133 /* devices */ 134 #define SECTORSIZE 512 135 136 #define NAND_ALLOW_ERASE_ALL 137 #define ADDR_COLUMN 1 138 #define ADDR_PAGE 2 139 #define ADDR_COLUMN_PAGE 3 140 141 #define NAND_ChipID_UNKNOWN 0x00 142 #define NAND_MAX_FLOORS 1 143 #define NAND_MAX_CHIPS 1 144 #define NAND_NO_RB 1 145 #define CONFIG_SYS_NAND_WP 146 147 #define CONFIG_JFFS2_NAND 148 /* nand device jffs2 lives on */ 149 #define CONFIG_JFFS2_DEV "nand0" 150 /* start of jffs2 partition */ 151 #define CONFIG_JFFS2_PART_OFFSET 0x680000 152 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 153 /* partition */ 154 155 /* Environment information */ 156 #define CONFIG_BOOTDELAY 1 157 158 #define CONFIG_EXTRA_ENV_SETTINGS \ 159 "loadaddr=0x82000000\0" \ 160 "console=ttyS0,115200n8\0" \ 161 "videospec=omapfb:vram:2M,vram:4M\0" \ 162 "mmcargs=setenv bootargs console=${console} " \ 163 "video=${videospec} " \ 164 "root=/dev/mmcblk0p2 rw " \ 165 "rootfstype=ext3 rootwait\0" \ 166 "nandargs=setenv bootargs console=${console} " \ 167 "video=${videospec} " \ 168 "root=/dev/mtdblock4 rw " \ 169 "rootfstype=jffs2\0" \ 170 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 171 "bootscript=echo Running bootscript from mmc ...; " \ 172 "source ${loadaddr}\0" \ 173 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 174 "mmcboot=echo Booting from mmc ...; " \ 175 "run mmcargs; " \ 176 "bootm ${loadaddr}\0" \ 177 "nandboot=echo Booting from nand ...; " \ 178 "run nandargs; " \ 179 "nand read ${loadaddr} 280000 400000; " \ 180 "bootm ${loadaddr}\0" \ 181 182 #define CONFIG_BOOTCOMMAND \ 183 "if mmc init; then " \ 184 "if run loadbootscript; then " \ 185 "run bootscript; " \ 186 "else " \ 187 "if run loaduimage; then " \ 188 "run mmcboot; " \ 189 "else run nandboot; " \ 190 "fi; " \ 191 "fi; " \ 192 "else run nandboot; fi" 193 194 #define CONFIG_AUTO_COMPLETE 1 195 /* 196 * Miscellaneous configurable options 197 */ 198 #define V_PROMPT "Pandora # " 199 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 201 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 203 #define CONFIG_SYS_PROMPT V_PROMPT 204 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 205 /* Print Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 207 sizeof(CONFIG_SYS_PROMPT) + 16) 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 209 /* args */ 210 /* Boot Argument Buffer Size */ 211 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 212 /* memtest works on */ 213 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 214 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 215 0x01F00000) /* 31MB */ 216 217 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 218 /* address */ 219 220 /* 221 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 222 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 223 */ 224 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 225 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ 226 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) 227 228 /*----------------------------------------------------------------------- 229 * Stack sizes 230 * 231 * The stack sizes are set up in start.S using the settings below 232 */ 233 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 234 #ifdef CONFIG_USE_IRQ 235 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 236 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 237 #endif 238 239 /*----------------------------------------------------------------------- 240 * Physical Memory Map 241 */ 242 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 243 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 244 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 245 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 246 247 /* SDRAM Bank Allocation method */ 248 #define SDRC_R_B_C 1 249 250 /*----------------------------------------------------------------------- 251 * FLASH and environment organization 252 */ 253 254 /* **** PISMO SUPPORT *** */ 255 256 /* Configure the PISMO */ 257 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 258 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 259 260 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 261 /* one chip */ 262 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 263 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 264 265 #define CONFIG_SYS_FLASH_BASE boot_flash_base 266 267 /* Monitor at start of flash */ 268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 269 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 270 271 #define CONFIG_ENV_IS_IN_NAND 1 272 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 273 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 274 275 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 276 #define CONFIG_ENV_OFFSET boot_flash_off 277 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 278 279 /*----------------------------------------------------------------------- 280 * CFI FLASH driver setup 281 */ 282 /* timeout values are in ticks */ 283 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 284 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 285 286 /* Flash banks JFFS2 should use */ 287 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 288 CONFIG_SYS_MAX_NAND_DEVICE) 289 #define CONFIG_SYS_JFFS2_MEM_NAND 290 /* use flash_info[2] */ 291 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 292 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 293 294 #ifndef __ASSEMBLY__ 295 extern gpmc_csx_t *nand_cs_base; 296 extern gpmc_t *gpmc_cfg_base; 297 extern unsigned int boot_flash_base; 298 extern volatile unsigned int boot_flash_env_addr; 299 extern unsigned int boot_flash_off; 300 extern unsigned int boot_flash_sec; 301 extern unsigned int boot_flash_type; 302 #endif 303 304 305 #define WRITE_NAND_COMMAND(d, adr)\ 306 writel(d, &nand_cs_base->nand_cmd) 307 #define WRITE_NAND_ADDRESS(d, adr)\ 308 writel(d, &nand_cs_base->nand_adr) 309 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) 310 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat) 311 312 /* Other NAND Access APIs */ 313 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ 314 while (0) 315 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ 316 while (0) 317 #define NAND_DISABLE_CE(nand) 318 #define NAND_ENABLE_CE(nand) 319 #define NAND_WAIT_READY(nand) udelay(10) 320 321 #endif /* __CONFIG_H */ 322