1 /* 2 * (C) Copyright 2008 3 * Grazvydas Ignotas <notasas@gmail.com> 4 * 5 * Configuration settings for the OMAP3 Pandora. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 #include <asm/sizes.h> 26 27 /* 28 * High Level Configuration Options 29 */ 30 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 31 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 33 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 34 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap3.h> 38 39 /* Clock Defines */ 40 #define V_OSCK 26000000 /* Clock output from T2 */ 41 #define V_SCLK (V_OSCK >> 1) 42 43 #undef CONFIG_USE_IRQ /* no support for IRQs */ 44 #define CONFIG_MISC_INIT_R 45 46 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 47 #define CONFIG_SETUP_MEMORY_TAGS 1 48 #define CONFIG_INITRD_TAG 1 49 #define CONFIG_REVISION_TAG 1 50 51 /* 52 * Size of malloc() pool 53 */ 54 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 55 /* Sector */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 57 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 58 /* initial data */ 59 60 /* 61 * Hardware drivers 62 */ 63 64 /* 65 * NS16550 Configuration 66 */ 67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 68 69 #define CONFIG_SYS_NS16550 70 #define CONFIG_SYS_NS16550_SERIAL 71 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 72 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 73 74 /* 75 * select serial console configuration 76 */ 77 #define CONFIG_CONS_INDEX 3 78 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 79 #define CONFIG_SERIAL3 3 80 81 /* allow to overwrite serial and ethaddr */ 82 #define CONFIG_ENV_OVERWRITE 83 #define CONFIG_BAUDRATE 115200 84 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 85 115200} 86 #define CONFIG_MMC 1 87 #define CONFIG_OMAP3_MMC 1 88 #define CONFIG_DOS_PARTITION 1 89 90 /* commands to include */ 91 #include <config_cmd_default.h> 92 93 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 94 #define CONFIG_CMD_FAT /* FAT support */ 95 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 96 97 #define CONFIG_CMD_I2C /* I2C serial bus support */ 98 #define CONFIG_CMD_MMC /* MMC support */ 99 #define CONFIG_CMD_NAND /* NAND support */ 100 101 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 102 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 103 #undef CONFIG_CMD_IMI /* iminfo */ 104 #undef CONFIG_CMD_IMLS /* List all found images */ 105 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 106 #undef CONFIG_CMD_NFS /* NFS support */ 107 108 #define CONFIG_SYS_NO_FLASH 109 #define CONFIG_SYS_I2C_SPEED 100000 110 #define CONFIG_SYS_I2C_SLAVE 1 111 #define CONFIG_SYS_I2C_BUS 0 112 #define CONFIG_SYS_I2C_BUS_SELECT 1 113 #define CONFIG_DRIVER_OMAP34XX_I2C 1 114 115 /* 116 * Board NAND Info. 117 */ 118 #define CONFIG_NAND_OMAP_GPMC 119 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 120 /* to access nand */ 121 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 122 /* to access nand */ 123 /* at CS0 */ 124 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 125 126 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 127 /* devices */ 128 #define SECTORSIZE 512 129 130 #define NAND_ALLOW_ERASE_ALL 131 #define ADDR_COLUMN 1 132 #define ADDR_PAGE 2 133 #define ADDR_COLUMN_PAGE 3 134 135 #define NAND_ChipID_UNKNOWN 0x00 136 #define NAND_MAX_FLOORS 1 137 #define NAND_MAX_CHIPS 1 138 #define NAND_NO_RB 1 139 #define CONFIG_SYS_NAND_WP 140 141 #define CONFIG_JFFS2_NAND 142 /* nand device jffs2 lives on */ 143 #define CONFIG_JFFS2_DEV "nand0" 144 /* start of jffs2 partition */ 145 #define CONFIG_JFFS2_PART_OFFSET 0x680000 146 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 147 /* partition */ 148 149 /* Environment information */ 150 #define CONFIG_BOOTDELAY 1 151 152 #define CONFIG_EXTRA_ENV_SETTINGS \ 153 "loadaddr=0x82000000\0" \ 154 "console=ttyS0,115200n8\0" \ 155 "videospec=omapfb:vram:2M,vram:4M\0" \ 156 "mmcargs=setenv bootargs console=${console} " \ 157 "video=${videospec} " \ 158 "root=/dev/mmcblk0p2 rw " \ 159 "rootfstype=ext3 rootwait\0" \ 160 "nandargs=setenv bootargs console=${console} " \ 161 "video=${videospec} " \ 162 "root=/dev/mtdblock4 rw " \ 163 "rootfstype=jffs2\0" \ 164 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 165 "bootscript=echo Running bootscript from mmc ...; " \ 166 "autoscr ${loadaddr}\0" \ 167 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 168 "mmcboot=echo Booting from mmc ...; " \ 169 "run mmcargs; " \ 170 "bootm ${loadaddr}\0" \ 171 "nandboot=echo Booting from nand ...; " \ 172 "run nandargs; " \ 173 "nand read ${loadaddr} 280000 400000; " \ 174 "bootm ${loadaddr}\0" \ 175 176 #define CONFIG_BOOTCOMMAND \ 177 "if mmcinit; then " \ 178 "if run loadbootscript; then " \ 179 "run bootscript; " \ 180 "else " \ 181 "if run loaduimage; then " \ 182 "run mmcboot; " \ 183 "else run nandboot; " \ 184 "fi; " \ 185 "fi; " \ 186 "else run nandboot; fi" 187 188 #define CONFIG_AUTO_COMPLETE 1 189 /* 190 * Miscellaneous configurable options 191 */ 192 #define V_PROMPT "Pandora # " 193 194 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 195 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 196 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 197 #define CONFIG_SYS_PROMPT V_PROMPT 198 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 199 /* Print Buffer Size */ 200 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 201 sizeof(CONFIG_SYS_PROMPT) + 16) 202 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 203 /* args */ 204 /* Boot Argument Buffer Size */ 205 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 206 /* memtest works on */ 207 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 208 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 209 0x01F00000) /* 31MB */ 210 211 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 212 /* address */ 213 214 /* 215 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 216 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 217 */ 218 #define V_PVT 7 219 220 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 221 #define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ 222 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) 223 224 /*----------------------------------------------------------------------- 225 * Stack sizes 226 * 227 * The stack sizes are set up in start.S using the settings below 228 */ 229 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 230 #ifdef CONFIG_USE_IRQ 231 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 232 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 233 #endif 234 235 /*----------------------------------------------------------------------- 236 * Physical Memory Map 237 */ 238 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 239 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 240 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 241 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 242 243 /* SDRAM Bank Allocation method */ 244 #define SDRC_R_B_C 1 245 246 /*----------------------------------------------------------------------- 247 * FLASH and environment organization 248 */ 249 250 /* **** PISMO SUPPORT *** */ 251 252 /* Configure the PISMO */ 253 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 254 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 255 256 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 257 /* one chip */ 258 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 259 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 260 261 #define CONFIG_SYS_FLASH_BASE boot_flash_base 262 263 /* Monitor at start of flash */ 264 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 265 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 266 267 #define CONFIG_ENV_IS_IN_NAND 1 268 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 269 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 270 271 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 272 #define CONFIG_ENV_OFFSET boot_flash_off 273 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 274 275 /*----------------------------------------------------------------------- 276 * CFI FLASH driver setup 277 */ 278 /* timeout values are in ticks */ 279 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 280 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 281 282 /* Flash banks JFFS2 should use */ 283 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 284 CONFIG_SYS_MAX_NAND_DEVICE) 285 #define CONFIG_SYS_JFFS2_MEM_NAND 286 /* use flash_info[2] */ 287 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 288 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 289 290 #ifndef __ASSEMBLY__ 291 extern gpmc_csx_t *nand_cs_base; 292 extern gpmc_t *gpmc_cfg_base; 293 extern unsigned int boot_flash_base; 294 extern volatile unsigned int boot_flash_env_addr; 295 extern unsigned int boot_flash_off; 296 extern unsigned int boot_flash_sec; 297 extern unsigned int boot_flash_type; 298 #endif 299 300 301 #define WRITE_NAND_COMMAND(d, adr)\ 302 writel(d, &nand_cs_base->nand_cmd) 303 #define WRITE_NAND_ADDRESS(d, adr)\ 304 writel(d, &nand_cs_base->nand_adr) 305 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) 306 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat) 307 308 /* Other NAND Access APIs */ 309 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ 310 while (0) 311 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ 312 while (0) 313 #define NAND_DISABLE_CE(nand) 314 #define NAND_ENABLE_CE(nand) 315 #define NAND_WAIT_READY(nand) udelay(10) 316 317 #endif /* __CONFIG_H */ 318