xref: /rk3399_rockchip-uboot/include/configs/omap3_pandora.h (revision 6cbec7b3bafc9f63cead2cc264505bcca36a074a)
12be2c6ccSDirk Behme /*
273225245SGrazvydas Ignotas  * (C) Copyright 2008-2010
373225245SGrazvydas Ignotas  * Gražvydas Ignotas <notasas@gmail.com>
42be2c6ccSDirk Behme  *
52be2c6ccSDirk Behme  * Configuration settings for the OMAP3 Pandora.
62be2c6ccSDirk Behme  *
72be2c6ccSDirk Behme  * This program is free software; you can redistribute it and/or
82be2c6ccSDirk Behme  * modify it under the terms of the GNU General Public License as
92be2c6ccSDirk Behme  * published by the Free Software Foundation; either version 2 of
102be2c6ccSDirk Behme  * the License, or (at your option) any later version.
112be2c6ccSDirk Behme  *
122be2c6ccSDirk Behme  * This program is distributed in the hope that it will be useful,
132be2c6ccSDirk Behme  * but WITHOUT ANY WARRANTY; without even the implied warranty of
142be2c6ccSDirk Behme  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
152be2c6ccSDirk Behme  * GNU General Public License for more details.
162be2c6ccSDirk Behme  *
172be2c6ccSDirk Behme  * You should have received a copy of the GNU General Public License
182be2c6ccSDirk Behme  * along with this program; if not, write to the Free Software
192be2c6ccSDirk Behme  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
202be2c6ccSDirk Behme  * MA 02111-1307 USA
212be2c6ccSDirk Behme  */
222be2c6ccSDirk Behme 
232be2c6ccSDirk Behme #ifndef __CONFIG_H
242be2c6ccSDirk Behme #define __CONFIG_H
252be2c6ccSDirk Behme 
262be2c6ccSDirk Behme /*
272be2c6ccSDirk Behme  * High Level Configuration Options
282be2c6ccSDirk Behme  */
29f56348afSSteve Sakoman #define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
302be2c6ccSDirk Behme #define CONFIG_OMAP		1	/* in a TI OMAP core */
312be2c6ccSDirk Behme #define CONFIG_OMAP34XX		1	/* which is a 34XX */
322be2c6ccSDirk Behme #define CONFIG_OMAP3430		1	/* which is in a 3430 */
332be2c6ccSDirk Behme #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
342be2c6ccSDirk Behme 
35cae377b5SVaibhav Hiremath #define CONFIG_SDRC	/* The chip has SDRC controller */
36cae377b5SVaibhav Hiremath 
372be2c6ccSDirk Behme #include <asm/arch/cpu.h>	/* get chip and board defs */
382be2c6ccSDirk Behme #include <asm/arch/omap3.h>
392be2c6ccSDirk Behme 
406a6b62e3SSanjeev Premi /*
416a6b62e3SSanjeev Premi  * Display CPU and Board information
426a6b62e3SSanjeev Premi  */
436a6b62e3SSanjeev Premi #define CONFIG_DISPLAY_CPUINFO		1
446a6b62e3SSanjeev Premi #define CONFIG_DISPLAY_BOARDINFO	1
456a6b62e3SSanjeev Premi 
462be2c6ccSDirk Behme /* Clock Defines */
472be2c6ccSDirk Behme #define V_OSCK			26000000	/* Clock output from T2 */
482be2c6ccSDirk Behme #define V_SCLK			(V_OSCK >> 1)
492be2c6ccSDirk Behme 
502be2c6ccSDirk Behme #undef CONFIG_USE_IRQ		/* no support for IRQs */
512be2c6ccSDirk Behme #define CONFIG_MISC_INIT_R
522be2c6ccSDirk Behme 
532be2c6ccSDirk Behme #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
542be2c6ccSDirk Behme #define CONFIG_SETUP_MEMORY_TAGS	1
552be2c6ccSDirk Behme #define CONFIG_INITRD_TAG		1
562be2c6ccSDirk Behme #define CONFIG_REVISION_TAG		1
572be2c6ccSDirk Behme 
582be2c6ccSDirk Behme /*
592be2c6ccSDirk Behme  * Size of malloc() pool
602be2c6ccSDirk Behme  */
619c44ddccSSandeep Paulraj #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
6273225245SGrazvydas Ignotas #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
632be2c6ccSDirk Behme 
642be2c6ccSDirk Behme /*
652be2c6ccSDirk Behme  * Hardware drivers
662be2c6ccSDirk Behme  */
672be2c6ccSDirk Behme 
6873225245SGrazvydas Ignotas #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
6973225245SGrazvydas Ignotas #define CONFIG_SYS_DEVICE_NULLDEV	1
7073225245SGrazvydas Ignotas 
7173225245SGrazvydas Ignotas /* USB */
7273225245SGrazvydas Ignotas #define CONFIG_MUSB_UDC			1
7373225245SGrazvydas Ignotas #define CONFIG_USB_OMAP3		1
7473225245SGrazvydas Ignotas #define CONFIG_TWL4030_USB		1
7573225245SGrazvydas Ignotas 
7673225245SGrazvydas Ignotas /* USB device configuration */
7773225245SGrazvydas Ignotas #define CONFIG_USB_DEVICE		1
7873225245SGrazvydas Ignotas #define CONFIG_USB_TTY			1
7973225245SGrazvydas Ignotas 
802be2c6ccSDirk Behme /*
812be2c6ccSDirk Behme  * NS16550 Configuration
822be2c6ccSDirk Behme  */
832be2c6ccSDirk Behme #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
842be2c6ccSDirk Behme 
852be2c6ccSDirk Behme #define CONFIG_SYS_NS16550
862be2c6ccSDirk Behme #define CONFIG_SYS_NS16550_SERIAL
872be2c6ccSDirk Behme #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
882be2c6ccSDirk Behme #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
892be2c6ccSDirk Behme 
902be2c6ccSDirk Behme /*
912be2c6ccSDirk Behme  * select serial console configuration
922be2c6ccSDirk Behme  */
932be2c6ccSDirk Behme #define CONFIG_CONS_INDEX		3
942be2c6ccSDirk Behme #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
952be2c6ccSDirk Behme #define CONFIG_SERIAL3			3
962be2c6ccSDirk Behme 
972be2c6ccSDirk Behme /* allow to overwrite serial and ethaddr */
982be2c6ccSDirk Behme #define CONFIG_ENV_OVERWRITE
992be2c6ccSDirk Behme #define CONFIG_BAUDRATE			115200
1002be2c6ccSDirk Behme #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
1012be2c6ccSDirk Behme 					115200}
1022be2c6ccSDirk Behme #define CONFIG_MMC			1
1032be2c6ccSDirk Behme #define CONFIG_OMAP3_MMC		1
1042be2c6ccSDirk Behme #define CONFIG_DOS_PARTITION		1
1052be2c6ccSDirk Behme 
10630563a04SNishanth Menon /* DDR - I use Micron DDR */
10730563a04SNishanth Menon #define CONFIG_OMAP3_MICRON_DDR		1
10830563a04SNishanth Menon 
1092be2c6ccSDirk Behme /* commands to include */
1102be2c6ccSDirk Behme #include <config_cmd_default.h>
1112be2c6ccSDirk Behme 
1122be2c6ccSDirk Behme #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
1132be2c6ccSDirk Behme #define CONFIG_CMD_FAT		/* FAT support			*/
1142be2c6ccSDirk Behme 
1152be2c6ccSDirk Behme #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
1162be2c6ccSDirk Behme #define CONFIG_CMD_MMC		/* MMC support			*/
1172be2c6ccSDirk Behme #define CONFIG_CMD_NAND		/* NAND support			*/
11873225245SGrazvydas Ignotas #define CONFIG_CMD_CACHE	/* Cache control		*/
1192be2c6ccSDirk Behme 
1202be2c6ccSDirk Behme #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
1212be2c6ccSDirk Behme #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
1222be2c6ccSDirk Behme #undef CONFIG_CMD_IMI		/* iminfo			*/
1232be2c6ccSDirk Behme #undef CONFIG_CMD_IMLS		/* List all found images	*/
1242be2c6ccSDirk Behme #undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
1252be2c6ccSDirk Behme #undef CONFIG_CMD_NFS		/* NFS support			*/
1262be2c6ccSDirk Behme 
1272be2c6ccSDirk Behme #define CONFIG_SYS_NO_FLASH
1280297ec7eSTom Rix #define CONFIG_HARD_I2C			1
1292be2c6ccSDirk Behme #define CONFIG_SYS_I2C_SPEED		100000
1302be2c6ccSDirk Behme #define CONFIG_SYS_I2C_SLAVE		1
1312be2c6ccSDirk Behme #define CONFIG_SYS_I2C_BUS		0
1322be2c6ccSDirk Behme #define CONFIG_SYS_I2C_BUS_SELECT	1
1332be2c6ccSDirk Behme #define CONFIG_DRIVER_OMAP34XX_I2C	1
1342be2c6ccSDirk Behme 
1352be2c6ccSDirk Behme /*
1362c155130STom Rix  * TWL4030
1372c155130STom Rix  */
1382c155130STom Rix #define CONFIG_TWL4030_POWER		1
1392c155130STom Rix #define CONFIG_TWL4030_LED		1
1402c155130STom Rix 
1412c155130STom Rix /*
1422be2c6ccSDirk Behme  * Board NAND Info.
1432be2c6ccSDirk Behme  */
1442be2c6ccSDirk Behme #define CONFIG_NAND_OMAP_GPMC
1452be2c6ccSDirk Behme #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
1462be2c6ccSDirk Behme 							/* to access nand */
1472be2c6ccSDirk Behme #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
1482be2c6ccSDirk Behme 							/* to access nand */
1492be2c6ccSDirk Behme 							/* at CS0 */
1502be2c6ccSDirk Behme #define GPMC_NAND_ECC_LP_x16_LAYOUT	1
1512be2c6ccSDirk Behme 
1522be2c6ccSDirk Behme #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
1532be2c6ccSDirk Behme 						/* devices */
15473225245SGrazvydas Ignotas 
15573225245SGrazvydas Ignotas #ifdef CONFIG_CMD_NAND
15673225245SGrazvydas Ignotas #define CONFIG_CMD_MTDPARTS
15773225245SGrazvydas Ignotas #define CONFIG_MTD_PARTITIONS
15873225245SGrazvydas Ignotas #define CONFIG_MTD_DEVICE
15973225245SGrazvydas Ignotas #define CONFIG_CMD_UBI
16073225245SGrazvydas Ignotas #define CONFIG_CMD_UBIFS
16173225245SGrazvydas Ignotas #define CONFIG_RBTREE
16273225245SGrazvydas Ignotas #define CONFIG_LZO
16373225245SGrazvydas Ignotas 
16473225245SGrazvydas Ignotas #define MTDIDS_DEFAULT			"nand0=nand"
16573225245SGrazvydas Ignotas #define MTDPARTS_DEFAULT		"mtdparts=nand:512k(xloader),"\
16673225245SGrazvydas Ignotas 					"1920k(uboot),128k(uboot-env),"\
16773225245SGrazvydas Ignotas 					"10m(boot),-(rootfs)"
16873225245SGrazvydas Ignotas #else
16973225245SGrazvydas Ignotas #define MTDPARTS_DEFAULT
17073225245SGrazvydas Ignotas #endif
1712be2c6ccSDirk Behme 
1722be2c6ccSDirk Behme /* Environment information */
1732be2c6ccSDirk Behme #define CONFIG_BOOTDELAY		1
1742be2c6ccSDirk Behme 
1752be2c6ccSDirk Behme #define CONFIG_EXTRA_ENV_SETTINGS \
17673225245SGrazvydas Ignotas 	"usbtty=cdc_acm\0" \
1772be2c6ccSDirk Behme 	"loadaddr=0x82000000\0" \
17873225245SGrazvydas Ignotas 	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
17973225245SGrazvydas Ignotas 	"rw rootflags=bulk_read console=ttyS0,115200n8 " \
18073225245SGrazvydas Ignotas 	"vram=6272K omapfb.vram=0:3000K\0" \
18173225245SGrazvydas Ignotas 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
1822be2c6ccSDirk Behme 
1832be2c6ccSDirk Behme #define CONFIG_BOOTCOMMAND \
18473225245SGrazvydas Ignotas 	"if mmc init && fatload mmc1 0 ${loadaddr} autoboot.scr || " \
18573225245SGrazvydas Ignotas 			"ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
18673225245SGrazvydas Ignotas 		"source ${loadaddr}; " \
1872be2c6ccSDirk Behme 	"fi; " \
18873225245SGrazvydas Ignotas 	"ubi part boot && ubifsmount boot && ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
1892be2c6ccSDirk Behme 
1902be2c6ccSDirk Behme #define CONFIG_AUTO_COMPLETE	1
1912be2c6ccSDirk Behme /*
1922be2c6ccSDirk Behme  * Miscellaneous configurable options
1932be2c6ccSDirk Behme  */
1942be2c6ccSDirk Behme #define CONFIG_SYS_LONGHELP		/* undef to save memory */
1952be2c6ccSDirk Behme #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
1962be2c6ccSDirk Behme #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
1971270ec13SRobert P. J. Day #define CONFIG_SYS_PROMPT		"Pandora # "
1982be2c6ccSDirk Behme #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
1992be2c6ccSDirk Behme /* Print Buffer Size */
2002be2c6ccSDirk Behme #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
2012be2c6ccSDirk Behme 					sizeof(CONFIG_SYS_PROMPT) + 16)
2022be2c6ccSDirk Behme #define CONFIG_SYS_MAXARGS		16	/* max number of command */
2032be2c6ccSDirk Behme 						/* args */
2042be2c6ccSDirk Behme /* Boot Argument Buffer Size */
2052be2c6ccSDirk Behme #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
2062be2c6ccSDirk Behme /* memtest works on */
2072be2c6ccSDirk Behme #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
2082be2c6ccSDirk Behme #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
2092be2c6ccSDirk Behme 					0x01F00000) /* 31MB */
2102be2c6ccSDirk Behme 
2112be2c6ccSDirk Behme #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
2122be2c6ccSDirk Behme 								/* address */
2132be2c6ccSDirk Behme 
2142be2c6ccSDirk Behme /*
215d3a513c2SManikandan Pillai  * OMAP3 has 12 GP timers, they can be driven by the system clock
216d3a513c2SManikandan Pillai  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
217d3a513c2SManikandan Pillai  * This rate is divided by a local divisor.
2182be2c6ccSDirk Behme  */
219d3a513c2SManikandan Pillai #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
220d3a513c2SManikandan Pillai #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
221d3a513c2SManikandan Pillai #define CONFIG_SYS_HZ			1000
2222be2c6ccSDirk Behme 
2232be2c6ccSDirk Behme /*-----------------------------------------------------------------------
2242be2c6ccSDirk Behme  * Stack sizes
2252be2c6ccSDirk Behme  *
2262be2c6ccSDirk Behme  * The stack sizes are set up in start.S using the settings below
2272be2c6ccSDirk Behme  */
2289c44ddccSSandeep Paulraj #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
2292be2c6ccSDirk Behme #ifdef CONFIG_USE_IRQ
2309c44ddccSSandeep Paulraj #define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
2319c44ddccSSandeep Paulraj #define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
2322be2c6ccSDirk Behme #endif
2332be2c6ccSDirk Behme 
2342be2c6ccSDirk Behme /*-----------------------------------------------------------------------
2352be2c6ccSDirk Behme  * Physical Memory Map
2362be2c6ccSDirk Behme  */
2372be2c6ccSDirk Behme #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
2382be2c6ccSDirk Behme #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
2399c44ddccSSandeep Paulraj #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
2402be2c6ccSDirk Behme #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
2412be2c6ccSDirk Behme 
2422be2c6ccSDirk Behme /* SDRAM Bank Allocation method */
2432be2c6ccSDirk Behme #define SDRC_R_B_C		1
2442be2c6ccSDirk Behme 
24523df4f69SGrazvydas Ignotas #define CONFIG_SYS_TEXT_BASE		0x80008000
24623df4f69SGrazvydas Ignotas #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
24723df4f69SGrazvydas Ignotas #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
24823df4f69SGrazvydas Ignotas #define CONFIG_SYS_INIT_RAM_SIZE	0x800
24923df4f69SGrazvydas Ignotas #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
25023df4f69SGrazvydas Ignotas 					CONFIG_SYS_INIT_RAM_SIZE - \
25123df4f69SGrazvydas Ignotas 					GENERATED_GBL_DATA_SIZE)
25223df4f69SGrazvydas Ignotas 
2532be2c6ccSDirk Behme /*-----------------------------------------------------------------------
2542be2c6ccSDirk Behme  * FLASH and environment organization
2552be2c6ccSDirk Behme  */
2562be2c6ccSDirk Behme 
2572be2c6ccSDirk Behme /* **** PISMO SUPPORT *** */
2582be2c6ccSDirk Behme 
2592be2c6ccSDirk Behme /* Configure the PISMO */
2602be2c6ccSDirk Behme #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
2612be2c6ccSDirk Behme #define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
2622be2c6ccSDirk Behme 
2639c44ddccSSandeep Paulraj #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
2642be2c6ccSDirk Behme 
265*6cbec7b3SLuca Ceresoli #if defined(CONFIG_CMD_NAND)
266*6cbec7b3SLuca Ceresoli #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
267*6cbec7b3SLuca Ceresoli #endif
2682be2c6ccSDirk Behme 
2692be2c6ccSDirk Behme /* Monitor at start of flash */
2702be2c6ccSDirk Behme #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
2712be2c6ccSDirk Behme 
2722be2c6ccSDirk Behme #define CONFIG_ENV_IS_IN_NAND		1
27373225245SGrazvydas Ignotas #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
2742be2c6ccSDirk Behme 
275*6cbec7b3SLuca Ceresoli #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
276*6cbec7b3SLuca Ceresoli #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
2772be2c6ccSDirk Behme #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
2782be2c6ccSDirk Behme 
2792be2c6ccSDirk Behme #endif				/* __CONFIG_H */
280