1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 27 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 28 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 29 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 30 #define CONFIG_OMAP3_OVERO 1 /* working with overo */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap3.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 1 39 #define CONFIG_DISPLAY_BOARDINFO 1 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #undef CONFIG_USE_IRQ /* no support for IRQs */ 46 #define CONFIG_MISC_INIT_R 47 48 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 49 #define CONFIG_SETUP_MEMORY_TAGS 1 50 #define CONFIG_INITRD_TAG 1 51 #define CONFIG_REVISION_TAG 1 52 53 /* 54 * Size of malloc() pool 55 */ 56 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 57 /* Sector */ 58 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 59 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 60 /* initial data */ 61 62 /* 63 * Hardware drivers 64 */ 65 66 /* 67 * NS16550 Configuration 68 */ 69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 70 71 #define CONFIG_SYS_NS16550 72 #define CONFIG_SYS_NS16550_SERIAL 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 75 76 /* 77 * select serial console configuration 78 */ 79 #define CONFIG_CONS_INDEX 3 80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 81 #define CONFIG_SERIAL3 3 82 83 /* allow to overwrite serial and ethaddr */ 84 #define CONFIG_ENV_OVERWRITE 85 #define CONFIG_BAUDRATE 115200 86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 87 115200} 88 #define CONFIG_MMC 1 89 #define CONFIG_OMAP3_MMC 1 90 #define CONFIG_DOS_PARTITION 1 91 92 /* commands to include */ 93 #include <config_cmd_default.h> 94 95 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 96 #define CONFIG_CMD_FAT /* FAT support */ 97 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 98 99 #define CONFIG_CMD_I2C /* I2C serial bus support */ 100 #define CONFIG_CMD_MMC /* MMC support */ 101 #define CONFIG_CMD_NAND /* NAND support */ 102 103 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 104 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 105 #undef CONFIG_CMD_IMI /* iminfo */ 106 #undef CONFIG_CMD_IMLS /* List all found images */ 107 #undef CONFIG_CMD_NFS /* NFS support */ 108 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 109 110 #define CONFIG_SYS_NO_FLASH 111 #define CONFIG_HARD_I2C 1 112 #define CONFIG_SYS_I2C_SPEED 100000 113 #define CONFIG_SYS_I2C_SLAVE 1 114 #define CONFIG_SYS_I2C_BUS 0 115 #define CONFIG_SYS_I2C_BUS_SELECT 1 116 #define CONFIG_DRIVER_OMAP34XX_I2C 1 117 118 /* 119 * TWL4030 120 */ 121 #define CONFIG_TWL4030_POWER 1 122 #define CONFIG_TWL4030_LED 1 123 124 /* 125 * Board NAND Info. 126 */ 127 #define CONFIG_NAND_OMAP_GPMC 128 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 129 /* to access nand */ 130 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 131 /* to access nand */ 132 /* at CS0 */ 133 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 134 135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 136 /* devices */ 137 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 138 139 #define CONFIG_JFFS2_NAND 140 /* nand device jffs2 lives on */ 141 #define CONFIG_JFFS2_DEV "nand0" 142 /* start of jffs2 partition */ 143 #define CONFIG_JFFS2_PART_OFFSET 0x680000 144 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 145 /* partition */ 146 147 /* Environment information */ 148 #define CONFIG_BOOTDELAY 5 149 150 #define CONFIG_EXTRA_ENV_SETTINGS \ 151 "loadaddr=0x82000000\0" \ 152 "console=ttyS2,115200n8\0" \ 153 "vram=12M\0" \ 154 "dvimode=1024x768MR-16@60\0" \ 155 "defaultdisplay=dvi\0" \ 156 "mmcroot=/dev/mmcblk0p2 rw\0" \ 157 "mmcrootfstype=ext3 rootwait\0" \ 158 "nandroot=/dev/mtdblock4 rw\0" \ 159 "nandrootfstype=jffs2\0" \ 160 "mmcargs=setenv bootargs console=${console} " \ 161 "vram=${vram} " \ 162 "omapfb.mode=dvi:${dvimode} " \ 163 "omapfb.debug=y " \ 164 "omapdss.def_disp=${defaultdisplay} " \ 165 "root=${mmcroot} " \ 166 "rootfstype=${mmcrootfstype}\0" \ 167 "nandargs=setenv bootargs console=${console} " \ 168 "vram=${vram} " \ 169 "omapfb.mode=dvi:${dvimode} " \ 170 "omapfb.debug=y " \ 171 "omapdss.def_disp=${defaultdisplay} " \ 172 "root=${nandroot} " \ 173 "rootfstype=${nandrootfstype}\0" \ 174 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 175 "bootscript=echo Running bootscript from mmc ...; " \ 176 "source ${loadaddr}\0" \ 177 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 178 "mmcboot=echo Booting from mmc ...; " \ 179 "run mmcargs; " \ 180 "bootm ${loadaddr}\0" \ 181 "nandboot=echo Booting from nand ...; " \ 182 "run nandargs; " \ 183 "nand read ${loadaddr} 280000 400000; " \ 184 "bootm ${loadaddr}\0" \ 185 186 #define CONFIG_BOOTCOMMAND \ 187 "if mmc init; then " \ 188 "if run loadbootscript; then " \ 189 "run bootscript; " \ 190 "else " \ 191 "if run loaduimage; then " \ 192 "run mmcboot; " \ 193 "else run nandboot; " \ 194 "fi; " \ 195 "fi; " \ 196 "else run nandboot; fi" 197 198 #define CONFIG_AUTO_COMPLETE 1 199 /* 200 * Miscellaneous configurable options 201 */ 202 #define V_PROMPT "Overo # " 203 204 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 205 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 206 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 207 #define CONFIG_SYS_PROMPT V_PROMPT 208 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 209 /* Print Buffer Size */ 210 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 211 sizeof(CONFIG_SYS_PROMPT) + 16) 212 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 213 /* args */ 214 /* Boot Argument Buffer Size */ 215 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 216 /* memtest works on */ 217 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 218 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 219 0x01F00000) /* 31MB */ 220 221 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 222 /* address */ 223 /* 224 * OMAP3 has 12 GP timers, they can be driven by the system clock 225 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 226 * This rate is divided by a local divisor. 227 */ 228 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 229 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 230 #define CONFIG_SYS_HZ 1000 231 232 /*----------------------------------------------------------------------- 233 * Stack sizes 234 * 235 * The stack sizes are set up in start.S using the settings below 236 */ 237 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 238 #ifdef CONFIG_USE_IRQ 239 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 240 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 241 #endif 242 243 /*----------------------------------------------------------------------- 244 * Physical Memory Map 245 */ 246 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 247 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 248 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 249 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 250 251 /* SDRAM Bank Allocation method */ 252 #define SDRC_R_B_C 1 253 254 /*----------------------------------------------------------------------- 255 * FLASH and environment organization 256 */ 257 258 /* **** PISMO SUPPORT *** */ 259 260 /* Configure the PISMO */ 261 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 262 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 263 264 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 265 /* one chip */ 266 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 267 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 268 269 #define CONFIG_SYS_FLASH_BASE boot_flash_base 270 271 /* Monitor at start of flash */ 272 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 273 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 274 275 #define CONFIG_ENV_IS_IN_NAND 1 276 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 277 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 278 279 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 280 #define CONFIG_ENV_OFFSET boot_flash_off 281 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 282 283 /*----------------------------------------------------------------------- 284 * CFI FLASH driver setup 285 */ 286 /* timeout values are in ticks */ 287 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 288 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 289 290 /* Flash banks JFFS2 should use */ 291 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 292 CONFIG_SYS_MAX_NAND_DEVICE) 293 #define CONFIG_SYS_JFFS2_MEM_NAND 294 /* use flash_info[2] */ 295 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 296 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 297 298 #ifndef __ASSEMBLY__ 299 extern struct gpmc *gpmc_cfg; 300 extern unsigned int boot_flash_base; 301 extern volatile unsigned int boot_flash_env_addr; 302 extern unsigned int boot_flash_off; 303 extern unsigned int boot_flash_sec; 304 extern unsigned int boot_flash_type; 305 #endif 306 307 #if defined(CONFIG_CMD_NET) 308 /*---------------------------------------------------------------------------- 309 * SMSC9211 Ethernet from SMSC9118 family 310 *---------------------------------------------------------------------------- 311 */ 312 313 #define CONFIG_NET_MULTI 314 #define CONFIG_SMC911X 1 315 #define CONFIG_SMC911X_32_BIT 316 #define CONFIG_SMC911X_BASE 0x2C000000 317 318 #endif /* (CONFIG_CMD_NET) */ 319 320 #endif /* __CONFIG_H */ 321