1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 11 #define CONFIG_NAND 12 13 #include <configs/ti_omap3_common.h> 14 /* 15 * We are only ever GP parts and will utilize all of the "downloaded image" 16 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). 17 */ 18 #undef CONFIG_SPL_TEXT_BASE 19 #define CONFIG_SPL_TEXT_BASE 0x40200000 20 21 #define CONFIG_BCH 22 23 /* Display CPU and Board information */ 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 /* call misc_init_r */ 27 #define CONFIG_MISC_INIT_R 28 29 /* pass the revision tag */ 30 #define CONFIG_REVISION_TAG 31 32 /* override size of malloc() pool */ 33 #undef CONFIG_SYS_MALLOC_LEN 34 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 35 /* Shift 128 << 15 provides 4 MiB heap to support UBI commands. 36 * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */ 37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15)) 38 39 /* I2C Support */ 40 #define CONFIG_SYS_I2C_OMAP34XX 41 42 /* TWL4030 LED */ 43 #define CONFIG_TWL4030_LED 44 45 /* USB EHCI */ 46 #define CONFIG_USB_EHCI 47 #define CONFIG_USB_EHCI_OMAP 48 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 49 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 50 51 /* Initialize GPIOs by default */ 52 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */ 53 #define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */ 54 #define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ 55 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */ 56 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ 57 58 /* commands to include */ 59 60 #ifdef CONFIG_NAND 61 #define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ 62 63 #define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ 64 #define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ 65 66 #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ 67 68 /* NAND block size is 128 KiB. Synchronize these values with 69 * overo_nand_partitions in mach-omap2/board-overo.c in Linux: 70 * xloader 4 * NAND_BLOCK_SIZE = 512 KiB 71 * uboot 14 * NAND_BLOCK_SIZE = 1792 KiB 72 * uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB 73 * linux 64 * NAND_BLOCK_SIZE = 8 MiB 74 * rootfs remainder 75 */ 76 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 77 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 78 "512k(xloader)," \ 79 "1792k(u-boot)," \ 80 "256k(environ)," \ 81 "8m(linux)," \ 82 "-(rootfs)" 83 #else /* CONFIG_NAND */ 84 #define MTDPARTS_DEFAULT 85 #endif /* CONFIG_NAND */ 86 87 /* Board NAND Info. */ 88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 89 /* to access nand */ 90 /* Environment information */ 91 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 DEFAULT_LINUX_BOOT_ENV \ 93 "bootdir=/boot\0" \ 94 "bootfile=zImage\0" \ 95 "usbtty=cdc_acm\0" \ 96 "console=ttyO2,115200n8\0" \ 97 "mpurate=auto\0" \ 98 "optargs=\0" \ 99 "vram=12M\0" \ 100 "dvimode=1024x768MR-16@60\0" \ 101 "defaultdisplay=dvi\0" \ 102 "mmcdev=0\0" \ 103 "mmcroot=/dev/mmcblk0p2 rw\0" \ 104 "mmcrootfstype=ext4 rootwait\0" \ 105 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 106 "nandrootfstype=ubifs\0" \ 107 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 108 "mmcargs=setenv bootargs console=${console} " \ 109 "${optargs} " \ 110 "mpurate=${mpurate} " \ 111 "vram=${vram} " \ 112 "omapfb.mode=dvi:${dvimode} " \ 113 "omapdss.def_disp=${defaultdisplay} " \ 114 "root=${mmcroot} " \ 115 "rootfstype=${mmcrootfstype}\0" \ 116 "nandargs=setenv bootargs console=${console} " \ 117 "${optargs} " \ 118 "mpurate=${mpurate} " \ 119 "vram=${vram} " \ 120 "omapfb.mode=dvi:${dvimode} " \ 121 "omapdss.def_disp=${defaultdisplay} " \ 122 "root=${nandroot} " \ 123 "rootfstype=${nandrootfstype}\0" \ 124 "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 125 "bootscript=echo Running boot script from mmc ...; " \ 126 "source ${loadaddr}\0" \ 127 "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ 128 "importbootenv=echo Importing environment from mmc ...; " \ 129 "env import -t ${loadaddr} ${filesize}\0" \ 130 "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ 131 "mmcboot=echo Booting from mmc...; " \ 132 "run mmcargs; " \ 133 "bootm ${loadaddr}\0" \ 134 "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ 135 "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ 136 "loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \ 137 "loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \ 138 "mmcbootfdt=echo Booting with DT from mmc ...; " \ 139 "run mmcargs; " \ 140 "bootz ${loadaddr} - ${fdtaddr}\0" \ 141 "nandboot=echo Booting from nand ...; " \ 142 "run nandargs; " \ 143 "if nand read ${loadaddr} linux; then " \ 144 "bootm ${loadaddr};" \ 145 "fi;\0" \ 146 "nanddtsboot=echo Booting from nand with DTS...; " \ 147 "run nandargs; " \ 148 "ubi part rootfs; "\ 149 "ubifsmount ubi0:rootfs; "\ 150 "run loadubifdt; "\ 151 "run loadubizimage; "\ 152 "bootz ${loadaddr} - ${fdtaddr}\0" \ 153 154 #define CONFIG_BOOTCOMMAND \ 155 "mmc dev ${mmcdev}; if mmc rescan; then " \ 156 "if run loadbootscript; then " \ 157 "run bootscript; " \ 158 "fi;" \ 159 "if run loadbootenv; then " \ 160 "echo Loaded environment from ${bootenv};" \ 161 "run importbootenv;" \ 162 "fi;" \ 163 "if test -n $uenvcmd; then " \ 164 "echo Running uenvcmd ...;" \ 165 "run uenvcmd;" \ 166 "fi;" \ 167 "if run loaduimage; then " \ 168 "run mmcboot;" \ 169 "fi;" \ 170 "if run loadzimage; then " \ 171 "if test -z \"${fdtfile}\"; then " \ 172 "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ 173 "fi;" \ 174 "if run loadfdt; then " \ 175 "run mmcbootfdt;" \ 176 "fi;" \ 177 "fi;" \ 178 "fi;" \ 179 "run nandboot; " \ 180 "if test -z \"${fdtfile}\"; then "\ 181 "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ 182 "fi;" \ 183 "run nanddtsboot; " \ 184 185 /* memtest works on */ 186 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 187 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 188 0x01F00000) /* 31MB */ 189 190 /* FLASH and environment organization */ 191 #if defined(CONFIG_NAND) 192 #define CONFIG_SYS_FLASH_BASE NAND_BASE 193 #endif 194 195 /* Monitor at start of flash */ 196 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 197 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 198 199 #define CONFIG_ENV_IS_IN_NAND 200 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 201 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 202 203 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 204 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 205 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 206 207 /* Configure SMSC9211 ethernet */ 208 #if defined(CONFIG_CMD_NET) 209 #define CONFIG_SMC911X 210 #define CONFIG_SMC911X_32_BIT 211 #define CONFIG_SMC911X_BASE 0x2C000000 212 #endif /* (CONFIG_CMD_NET) */ 213 214 /* Initial RAM setup */ 215 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 216 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 217 218 /* NAND boot config */ 219 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 220 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 221 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 222 #define CONFIG_SYS_NAND_PAGE_COUNT 64 223 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 224 #define CONFIG_SYS_NAND_OOBSIZE 64 225 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 227 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 228 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 229 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 230 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 231 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 232 52, 53, 54, 55, 56} 233 #define CONFIG_SYS_NAND_ECCSIZE 512 234 #define CONFIG_SYS_NAND_ECCBYTES 13 235 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 236 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 237 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 238 /* NAND: SPL falcon mode configs */ 239 #ifdef CONFIG_SPL_OS_BOOT 240 #define CONFIG_CMD_SPL_NAND_OFS 0x240000 241 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 242 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 243 #endif 244 245 #endif /* __CONFIG_H */ 246