1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Author : 5 * Manikandan Pillai <mani.pillai@ti.com> 6 * Derived from Beagle Board and 3430 SDP code by 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Syed Mohammed Khasim <khasim@ti.com> 9 * 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * 12 * Configuration settings for the TI OMAP3 EVM board. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_OMAP /* This is TI OMAP core */ 40 #define CONFIG_OMAP34XX /* belonging to 34XX family */ 41 #define CONFIG_OMAP3430 /* which is in a 3430 */ 42 43 #define CONFIG_SDRC /* The chip has SDRC controller */ 44 45 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ 46 #define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */ 47 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ 48 49 /* 50 * Get cpu and chip specific definitions 51 */ 52 #include <asm/arch/cpu.h> 53 #include <asm/arch/omap3.h> 54 55 #undef CONFIG_USE_IRQ /* no support for IRQs */ 56 57 /* 58 * Clock related definitions 59 */ 60 #define V_OSCK 26000000 /* Clock output from T2 */ 61 #define V_SCLK (V_OSCK >> 1) 62 63 /* 64 * OMAP3 has 12 GP timers, they can be driven by the system clock 65 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 66 * This rate is divided by a local divisor. 67 */ 68 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 69 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 70 #define CONFIG_SYS_HZ 1000 71 72 /* Size of environment - 128KB */ 73 #define CONFIG_ENV_SIZE (128 << 10) 74 75 /* Size of malloc pool */ 76 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 77 78 /* 79 * Stack sizes 80 * 81 * The stack sizes are set up in start.S using the settings below 82 */ 83 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 84 #ifdef CONFIG_USE_IRQ 85 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 86 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 87 #endif 88 89 /* 90 * Physical Memory Map 91 * Note 1: CS1 may or may not be populated 92 * Note 2: SDRAM size is expected to be at least 32MB 93 */ 94 #define CONFIG_NR_DRAM_BANKS 2 95 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 96 #define PHYS_SDRAM_1_SIZE (32 << 20) 97 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 98 99 /* SDRAM Bank Allocation method */ 100 #define SDRC_R_B_C 101 102 /* Limits for memtest */ 103 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 104 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 105 0x01F00000) /* 31MB */ 106 107 /* Default load address */ 108 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) 109 110 /* ----------------------------------------------------------------------------- 111 * Hardware drivers 112 * ----------------------------------------------------------------------------- 113 */ 114 115 /* 116 * NS16550 Configuration 117 */ 118 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 119 120 #define CONFIG_SYS_NS16550 121 #define CONFIG_SYS_NS16550_SERIAL 122 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 123 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 124 125 /* 126 * select serial console configuration 127 */ 128 #define CONFIG_CONS_INDEX 1 129 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 130 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 131 #define CONFIG_BAUDRATE 115200 132 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 133 115200} 134 135 /* 136 * I2C 137 */ 138 #define CONFIG_HARD_I2C 139 #define CONFIG_DRIVER_OMAP34XX_I2C 140 141 #define CONFIG_SYS_I2C_SPEED 100000 142 #define CONFIG_SYS_I2C_SLAVE 1 143 #define CONFIG_SYS_I2C_BUS 0 144 #define CONFIG_SYS_I2C_BUS_SELECT 1 145 146 /* 147 * PISMO support 148 */ 149 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 150 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 151 152 /* Monitor at start of flash - Reserve 2 sectors */ 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 154 155 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 156 157 /* Start location & size of environment */ 158 #define ONENAND_ENV_OFFSET 0x260000 159 #define SMNAND_ENV_OFFSET 0x260000 160 161 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 162 163 /* 164 * NAND 165 */ 166 /* Physical address to access NAND */ 167 #define CONFIG_SYS_NAND_ADDR NAND_BASE 168 169 /* Physical address to access NAND at CS0 */ 170 #define CONFIG_SYS_NAND_BASE NAND_BASE 171 172 /* Max number of NAND devices */ 173 #define CONFIG_SYS_MAX_NAND_DEVICE 1 174 175 /* Timeout values (in ticks) */ 176 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 177 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 178 179 /* Flash banks JFFS2 should use */ 180 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 181 CONFIG_SYS_MAX_NAND_DEVICE) 182 183 #define CONFIG_SYS_JFFS2_MEM_NAND 184 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 185 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 186 187 #define CONFIG_JFFS2_NAND 188 /* nand device jffs2 lives on */ 189 #define CONFIG_JFFS2_DEV "nand0" 190 /* Start of jffs2 partition */ 191 #define CONFIG_JFFS2_PART_OFFSET 0x680000 192 /* Size of jffs2 partition */ 193 #define CONFIG_JFFS2_PART_SIZE 0xf980000 194 195 /* 196 * MMC 197 */ 198 #define CONFIG_MMC 199 #define CONFIG_GENERIC_MMC 200 #define CONFIG_OMAP_HSMMC 201 #define CONFIG_DOS_PARTITION 202 203 /* USB 204 * 205 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 206 * Enable CONFIG_MUSB_UDD for Device functionalities. 207 */ 208 #define CONFIG_USB_OMAP3 209 #define CONFIG_MUSB_HCD 210 /* #define CONFIG_MUSB_UDC */ 211 212 #ifdef CONFIG_USB_OMAP3 213 214 #ifdef CONFIG_MUSB_HCD 215 #define CONFIG_CMD_USB 216 217 #define CONFIG_USB_STORAGE 218 #define CONGIG_CMD_STORAGE 219 #define CONFIG_CMD_FAT 220 221 #ifdef CONFIG_USB_KEYBOARD 222 #define CONFIG_SYS_USB_EVENT_POLL 223 #define CONFIG_PREBOOT "usb start" 224 #endif /* CONFIG_USB_KEYBOARD */ 225 226 #endif /* CONFIG_MUSB_HCD */ 227 228 #ifdef CONFIG_MUSB_UDC 229 /* USB device configuration */ 230 #define CONFIG_USB_DEVICE 231 #define CONFIG_USB_TTY 232 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 233 234 /* Change these to suit your needs */ 235 #define CONFIG_USBD_VENDORID 0x0451 236 #define CONFIG_USBD_PRODUCTID 0x5678 237 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 238 #define CONFIG_USBD_PRODUCT_NAME "EVM" 239 #endif /* CONFIG_MUSB_UDC */ 240 241 #endif /* CONFIG_USB_OMAP3 */ 242 243 /* ---------------------------------------------------------------------------- 244 * U-boot features 245 * ---------------------------------------------------------------------------- 246 */ 247 #define CONFIG_SYS_LONGHELP 248 #define CONFIG_SYS_HUSH_PARSER 249 #define CONFIG_SYS_PROMPT "OMAP3_EVM # " 250 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 251 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */ 252 253 /* Display CPU and Board information */ 254 #define CONFIG_DISPLAY_CPUINFO 255 #define CONFIG_DISPLAY_BOARDINFO 256 257 #define CONFIG_MISC_INIT_R 258 259 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 260 #define CONFIG_SETUP_MEMORY_TAGS 261 #define CONFIG_INITRD_TAG 262 #define CONFIG_REVISION_TAG 263 264 /* Allow to overwrite serial and ethaddr */ 265 #define CONFIG_ENV_OVERWRITE 266 267 /* Add auto-completion support */ 268 #define CONFIG_AUTO_COMPLETE 269 270 /* Size of Console IO buffer */ 271 #define CONFIG_SYS_CBSIZE 512 272 273 /* Size of print buffer */ 274 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 275 sizeof(CONFIG_SYS_PROMPT) + 16) 276 277 /* Size of bootarg buffer */ 278 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 279 280 /* Default commands to include */ 281 #include <config_cmd_default.h> 282 283 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 284 #define CONFIG_CMD_FAT /* FAT support */ 285 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 286 287 #define CONFIG_CMD_I2C /* I2C serial bus support */ 288 #define CONFIG_CMD_MMC /* MMC support */ 289 #define CONFIG_CMD_NAND /* NAND support */ 290 #define CONFIG_CMD_DHCP 291 #define CONFIG_CMD_PING 292 293 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 294 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 295 #undef CONFIG_CMD_IMI /* iminfo */ 296 #undef CONFIG_CMD_IMLS /* List all found images */ 297 298 /* 299 * Additional definitions that depend on chosen commands 300 */ 301 /* NAND */ 302 #if defined(CONFIG_CMD_NAND) 303 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 304 305 #define CONFIG_NAND_OMAP_GPMC 306 #define GPMC_NAND_ECC_LP_x16_LAYOUT 307 #define CONFIG_ENV_IS_IN_NAND 308 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 309 #elif defined(CONFIG_CMD_ONENAND) 310 #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE 311 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 312 313 #define CONFIG_ENV_IS_IN_ONENAND 314 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET 315 #endif 316 317 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 318 319 #if defined(CONFIG_CMD_NET) 320 321 /* Ethernet (SMSC9115 from SMSC9118 family) */ 322 #define CONFIG_SMC911X 323 #define CONFIG_SMC911X_32_BIT 324 #define CONFIG_SMC911X_BASE 0x2C000000 325 326 /* BOOTP fields */ 327 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 328 #define CONFIG_BOOTP_GATEWAY 0x00000002 329 #define CONFIG_BOOTP_HOSTNAME 0x00000004 330 #define CONFIG_BOOTP_BOOTPATH 0x00000010 331 332 #endif /* CONFIG_CMD_NET */ 333 334 /* Support for relocation */ 335 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 336 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 337 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 338 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 339 CONFIG_SYS_INIT_RAM_SIZE - \ 340 GENERATED_GBL_DATA_SIZE) 341 342 /* ----------------------------------------------------------------------------- 343 * Board specific 344 * ----------------------------------------------------------------------------- 345 */ 346 #define CONFIG_SYS_NO_FLASH 347 348 /* Uncomment to define the board revision statically */ 349 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ 350 351 /* ----------------------------------------------------------------------------- 352 * Default environment 353 * ----------------------------------------------------------------------------- 354 */ 355 #define CONFIG_BOOTDELAY 10 356 #define CONFIG_BOOTFILE "uImage" 357 358 #define CONFIG_EXTRA_ENV_SETTINGS \ 359 "loadaddr=0x82000000\0" \ 360 "usbtty=cdc_acm\0" \ 361 "mmcdev=0\0" \ 362 "console=ttyO0,115200n8\0" \ 363 "mmcargs=setenv bootargs console=${console} " \ 364 "root=/dev/mmcblk0p2 rw " \ 365 "rootfstype=ext3 rootwait\0" \ 366 "nandargs=setenv bootargs console=${console} " \ 367 "root=/dev/mtdblock4 rw " \ 368 "rootfstype=jffs2\0" \ 369 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 370 "bootscript=echo Running bootscript from mmc ...; " \ 371 "source ${loadaddr}\0" \ 372 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 373 "mmcboot=echo Booting from mmc ...; " \ 374 "run mmcargs; " \ 375 "bootm ${loadaddr}\0" \ 376 "nandboot=echo Booting from nand ...; " \ 377 "run nandargs; " \ 378 "onenand read ${loadaddr} 280000 400000; " \ 379 "bootm ${loadaddr}\0" \ 380 381 #define CONFIG_BOOTCOMMAND \ 382 "if mmc rescan ${mmcdev}; then " \ 383 "if run loadbootscript; then " \ 384 "run bootscript; " \ 385 "else " \ 386 "if run loaduimage; then " \ 387 "run mmcboot; " \ 388 "else run nandboot; " \ 389 "fi; " \ 390 "fi; " \ 391 "else run nandboot; fi" 392 393 #endif /* __CONFIG_H */ 394