1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Author : 5 * Manikandan Pillai <mani.pillai@ti.com> 6 * Derived from Beagle Board and 3430 SDP code by 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Syed Mohammed Khasim <khasim@ti.com> 9 * 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * 12 * Configuration settings for the TI OMAP3 EVM board. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 40 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 41 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 42 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 43 #define CONFIG_OMAP3_EVM 1 /* working with EVM */ 44 45 #include <asm/arch/cpu.h> /* get chip and board defs */ 46 #include <asm/arch/omap3.h> 47 48 /* 49 * Display CPU and Board information 50 */ 51 #define CONFIG_DISPLAY_CPUINFO 1 52 #define CONFIG_DISPLAY_BOARDINFO 1 53 54 /* Clock Defines */ 55 #define V_OSCK 26000000 /* Clock output from T2 */ 56 #define V_SCLK (V_OSCK >> 1) 57 58 #undef CONFIG_USE_IRQ /* no support for IRQs */ 59 #define CONFIG_MISC_INIT_R 60 61 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 62 #define CONFIG_SETUP_MEMORY_TAGS 1 63 #define CONFIG_INITRD_TAG 1 64 #define CONFIG_REVISION_TAG 1 65 66 /* 67 * Size of malloc() pool 68 */ 69 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 70 /* Sector */ 71 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 72 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 73 /* initial data */ 74 /* 75 * Hardware drivers 76 */ 77 78 /* 79 * NS16550 Configuration 80 */ 81 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 82 83 #define CONFIG_SYS_NS16550 84 #define CONFIG_SYS_NS16550_SERIAL 85 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 86 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 87 88 /* 89 * select serial console configuration 90 */ 91 #define CONFIG_CONS_INDEX 1 92 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 93 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 94 95 /* allow to overwrite serial and ethaddr */ 96 #define CONFIG_ENV_OVERWRITE 97 #define CONFIG_BAUDRATE 115200 98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 99 115200} 100 #define CONFIG_MMC 1 101 #define CONFIG_OMAP3_MMC 1 102 #define CONFIG_DOS_PARTITION 1 103 104 /* DDR - I use Micron DDR */ 105 #define CONFIG_OMAP3_MICRON_DDR 1 106 107 /* commands to include */ 108 #include <config_cmd_default.h> 109 110 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 111 #define CONFIG_CMD_FAT /* FAT support */ 112 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 113 114 #define CONFIG_CMD_I2C /* I2C serial bus support */ 115 #define CONFIG_CMD_MMC /* MMC support */ 116 #define CONFIG_CMD_ONENAND /* ONENAND support */ 117 #define CONFIG_CMD_DHCP 118 #define CONFIG_CMD_PING 119 120 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 121 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 122 #undef CONFIG_CMD_IMI /* iminfo */ 123 #undef CONFIG_CMD_IMLS /* List all found images */ 124 125 #define CONFIG_SYS_NO_FLASH 126 #define CONFIG_HARD_I2C 1 127 #define CONFIG_SYS_I2C_SPEED 100000 128 #define CONFIG_SYS_I2C_SLAVE 1 129 #define CONFIG_SYS_I2C_BUS 0 130 #define CONFIG_SYS_I2C_BUS_SELECT 1 131 #define CONFIG_DRIVER_OMAP34XX_I2C 1 132 133 /* 134 * TWL4030 135 */ 136 #define CONFIG_TWL4030_POWER 1 137 138 /* 139 * Board NAND Info. 140 */ 141 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 142 /* to access nand */ 143 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 144 /* to access */ 145 /* nand at CS0 */ 146 147 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 148 /* NAND devices */ 149 #define CONFIG_JFFS2_NAND 150 /* nand device jffs2 lives on */ 151 #define CONFIG_JFFS2_DEV "nand0" 152 /* start of jffs2 partition */ 153 #define CONFIG_JFFS2_PART_OFFSET 0x680000 154 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 155 156 /* Environment information */ 157 #define CONFIG_BOOTDELAY 10 158 159 #define CONFIG_BOOTFILE uImage 160 161 #define CONFIG_EXTRA_ENV_SETTINGS \ 162 "loadaddr=0x82000000\0" \ 163 "console=ttyS2,115200n8\0" \ 164 "mmcargs=setenv bootargs console=${console} " \ 165 "root=/dev/mmcblk0p2 rw " \ 166 "rootfstype=ext3 rootwait\0" \ 167 "nandargs=setenv bootargs console=${console} " \ 168 "root=/dev/mtdblock4 rw " \ 169 "rootfstype=jffs2\0" \ 170 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 171 "bootscript=echo Running bootscript from mmc ...; " \ 172 "source ${loadaddr}\0" \ 173 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 174 "mmcboot=echo Booting from mmc ...; " \ 175 "run mmcargs; " \ 176 "bootm ${loadaddr}\0" \ 177 "nandboot=echo Booting from nand ...; " \ 178 "run nandargs; " \ 179 "onenand read ${loadaddr} 280000 400000; " \ 180 "bootm ${loadaddr}\0" \ 181 182 #define CONFIG_BOOTCOMMAND \ 183 "if mmc init; then " \ 184 "if run loadbootscript; then " \ 185 "run bootscript; " \ 186 "else " \ 187 "if run loaduimage; then " \ 188 "run mmcboot; " \ 189 "else run nandboot; " \ 190 "fi; " \ 191 "fi; " \ 192 "else run nandboot; fi" 193 194 #define CONFIG_AUTO_COMPLETE 1 195 /* 196 * Miscellaneous configurable options 197 */ 198 #define V_PROMPT "OMAP3_EVM # " 199 200 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 201 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 203 #define CONFIG_SYS_PROMPT V_PROMPT 204 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 205 /* Print Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 207 sizeof(CONFIG_SYS_PROMPT) + 16) 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 209 /* args */ 210 /* Boot Argument Buffer Size */ 211 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 212 /* memtest works on */ 213 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 214 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 215 0x01F00000) /* 31MB */ 216 217 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 218 /* address */ 219 220 /* 221 * OMAP3 has 12 GP timers, they can be driven by the system clock 222 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 223 * This rate is divided by a local divisor. 224 */ 225 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 226 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 227 #define CONFIG_SYS_HZ 1000 228 229 /*----------------------------------------------------------------------- 230 * Stack sizes 231 * 232 * The stack sizes are set up in start.S using the settings below 233 */ 234 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 235 #ifdef CONFIG_USE_IRQ 236 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 237 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 238 #endif 239 240 /*----------------------------------------------------------------------- 241 * Physical Memory Map 242 */ 243 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 244 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 245 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 246 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 247 248 /* SDRAM Bank Allocation method */ 249 #define SDRC_R_B_C 1 250 251 /*----------------------------------------------------------------------- 252 * FLASH and environment organization 253 */ 254 255 /* **** PISMO SUPPORT *** */ 256 257 /* Configure the PISMO */ 258 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 259 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 260 261 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 262 /* on one chip */ 263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 265 266 #define CONFIG_SYS_FLASH_BASE boot_flash_base 267 268 /* Monitor at start of flash */ 269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 270 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 271 272 #define CONFIG_ENV_IS_IN_ONENAND 1 273 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 274 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 275 276 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 277 #define CONFIG_ENV_OFFSET boot_flash_off 278 #define CONFIG_ENV_ADDR boot_flash_env_addr 279 280 /*----------------------------------------------------------------------- 281 * CFI FLASH driver setup 282 */ 283 /* timeout values are in ticks */ 284 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 285 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 286 287 /* Flash banks JFFS2 should use */ 288 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 289 CONFIG_SYS_MAX_NAND_DEVICE) 290 #define CONFIG_SYS_JFFS2_MEM_NAND 291 /* use flash_info[2] */ 292 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 293 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 294 295 #ifndef __ASSEMBLY__ 296 extern struct gpmc *gpmc_cfg; 297 extern unsigned int boot_flash_base; 298 extern volatile unsigned int boot_flash_env_addr; 299 extern unsigned int boot_flash_off; 300 extern unsigned int boot_flash_sec; 301 extern unsigned int boot_flash_type; 302 #endif 303 304 /*---------------------------------------------------------------------------- 305 * SMSC9115 Ethernet from SMSC9118 family 306 *---------------------------------------------------------------------------- 307 */ 308 #if defined(CONFIG_CMD_NET) 309 310 #define CONFIG_NET_MULTI 311 #define CONFIG_SMC911X 312 #define CONFIG_SMC911X_32_BIT 313 #define CONFIG_SMC911X_BASE 0x2C000000 314 315 #endif /* (CONFIG_CMD_NET) */ 316 317 /* 318 * BOOTP fields 319 */ 320 321 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 322 #define CONFIG_BOOTP_GATEWAY 0x00000002 323 #define CONFIG_BOOTP_HOSTNAME 0x00000004 324 #define CONFIG_BOOTP_BOOTPATH 0x00000010 325 326 #endif /* __CONFIG_H */ 327