1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Author : 5 * Manikandan Pillai <mani.pillai@ti.com> 6 * Derived from Beagle Board and 3430 SDP code by 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Syed Mohammed Khasim <khasim@ti.com> 9 * 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * 12 * Configuration settings for the TI OMAP3 EVM board. 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 40 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 41 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 42 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 43 #define CONFIG_OMAP3_EVM 1 /* working with EVM */ 44 45 #include <asm/arch/cpu.h> /* get chip and board defs */ 46 #include <asm/arch/omap3.h> 47 48 /* 49 * Display CPU and Board information 50 */ 51 #define CONFIG_DISPLAY_CPUINFO 1 52 #define CONFIG_DISPLAY_BOARDINFO 1 53 54 /* Clock Defines */ 55 #define V_OSCK 26000000 /* Clock output from T2 */ 56 #define V_SCLK (V_OSCK >> 1) 57 58 #undef CONFIG_USE_IRQ /* no support for IRQs */ 59 #define CONFIG_MISC_INIT_R 60 61 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 62 #define CONFIG_SETUP_MEMORY_TAGS 1 63 #define CONFIG_INITRD_TAG 1 64 #define CONFIG_REVISION_TAG 1 65 66 /* 67 * Size of malloc() pool 68 */ 69 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 70 /* Sector */ 71 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 72 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 73 /* initial data */ 74 /* 75 * Hardware drivers 76 */ 77 78 /* 79 * NS16550 Configuration 80 */ 81 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 82 83 #define CONFIG_SYS_NS16550 84 #define CONFIG_SYS_NS16550_SERIAL 85 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 86 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 87 88 /* 89 * select serial console configuration 90 */ 91 #define CONFIG_CONS_INDEX 1 92 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 93 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ 94 95 /* allow to overwrite serial and ethaddr */ 96 #define CONFIG_ENV_OVERWRITE 97 #define CONFIG_BAUDRATE 115200 98 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 99 115200} 100 #define CONFIG_MMC 1 101 #define CONFIG_OMAP3_MMC 1 102 #define CONFIG_DOS_PARTITION 1 103 104 /* DDR - I use Micron DDR */ 105 #define CONFIG_OMAP3_MICRON_DDR 1 106 107 /* USB 108 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard 109 * Enable CONFIG_MUSB_UDD for Device functionalities. 110 */ 111 #define CONFIG_USB_OMAP3 1 112 #define CONFIG_MUSB_HCD 1 113 /* #define CONFIG_MUSB_UDC 1 */ 114 115 #ifdef CONFIG_USB_OMAP3 116 117 #ifdef CONFIG_MUSB_HCD 118 #define CONFIG_CMD_USB 119 120 #define CONFIG_USB_STORAGE 121 #define CONGIG_CMD_STORAGE 122 #define CONFIG_CMD_FAT 123 124 #ifdef CONFIG_USB_KEYBOARD 125 #define CONFIG_SYS_USB_EVENT_POLL 126 #define CONFIG_PREBOOT "usb start" 127 #endif /* CONFIG_USB_KEYBOARD */ 128 129 #endif /* CONFIG_MUSB_HCD */ 130 131 #ifdef CONFIG_MUSB_UDC 132 /* USB device configuration */ 133 #define CONFIG_USB_DEVICE 1 134 #define CONFIG_USB_TTY 1 135 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 136 /* Change these to suit your needs */ 137 #define CONFIG_USBD_VENDORID 0x0451 138 #define CONFIG_USBD_PRODUCTID 0x5678 139 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 140 #define CONFIG_USBD_PRODUCT_NAME "EVM" 141 #endif /* CONFIG_MUSB_UDC */ 142 143 #endif /* CONFIG_USB_OMAP3 */ 144 145 /* commands to include */ 146 #include <config_cmd_default.h> 147 148 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 149 #define CONFIG_CMD_FAT /* FAT support */ 150 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 151 152 #define CONFIG_CMD_I2C /* I2C serial bus support */ 153 #define CONFIG_CMD_MMC /* MMC support */ 154 #define CONFIG_CMD_ONENAND /* ONENAND support */ 155 #define CONFIG_CMD_DHCP 156 #define CONFIG_CMD_PING 157 158 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 159 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 160 #undef CONFIG_CMD_IMI /* iminfo */ 161 #undef CONFIG_CMD_IMLS /* List all found images */ 162 163 #define CONFIG_SYS_NO_FLASH 164 #define CONFIG_HARD_I2C 1 165 #define CONFIG_SYS_I2C_SPEED 100000 166 #define CONFIG_SYS_I2C_SLAVE 1 167 #define CONFIG_SYS_I2C_BUS 0 168 #define CONFIG_SYS_I2C_BUS_SELECT 1 169 #define CONFIG_DRIVER_OMAP34XX_I2C 1 170 171 /* 172 * TWL4030 173 */ 174 #define CONFIG_TWL4030_POWER 1 175 176 /* 177 * Board NAND Info. 178 */ 179 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 180 /* to access nand */ 181 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 182 /* to access */ 183 /* nand at CS0 */ 184 185 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 186 /* NAND devices */ 187 #define CONFIG_JFFS2_NAND 188 /* nand device jffs2 lives on */ 189 #define CONFIG_JFFS2_DEV "nand0" 190 /* start of jffs2 partition */ 191 #define CONFIG_JFFS2_PART_OFFSET 0x680000 192 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 193 194 /* Environment information */ 195 #define CONFIG_BOOTDELAY 10 196 197 #define CONFIG_BOOTFILE uImage 198 199 #define CONFIG_EXTRA_ENV_SETTINGS \ 200 "loadaddr=0x82000000\0" \ 201 "usbtty=cdc_acm\0" \ 202 "console=ttyS2,115200n8\0" \ 203 "mmcargs=setenv bootargs console=${console} " \ 204 "root=/dev/mmcblk0p2 rw " \ 205 "rootfstype=ext3 rootwait\0" \ 206 "nandargs=setenv bootargs console=${console} " \ 207 "root=/dev/mtdblock4 rw " \ 208 "rootfstype=jffs2\0" \ 209 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 210 "bootscript=echo Running bootscript from mmc ...; " \ 211 "source ${loadaddr}\0" \ 212 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 213 "mmcboot=echo Booting from mmc ...; " \ 214 "run mmcargs; " \ 215 "bootm ${loadaddr}\0" \ 216 "nandboot=echo Booting from nand ...; " \ 217 "run nandargs; " \ 218 "onenand read ${loadaddr} 280000 400000; " \ 219 "bootm ${loadaddr}\0" \ 220 221 #define CONFIG_BOOTCOMMAND \ 222 "if mmc init; then " \ 223 "if run loadbootscript; then " \ 224 "run bootscript; " \ 225 "else " \ 226 "if run loaduimage; then " \ 227 "run mmcboot; " \ 228 "else run nandboot; " \ 229 "fi; " \ 230 "fi; " \ 231 "else run nandboot; fi" 232 233 #define CONFIG_AUTO_COMPLETE 1 234 /* 235 * Miscellaneous configurable options 236 */ 237 #define V_PROMPT "OMAP3_EVM # " 238 239 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 240 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 241 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 242 #define CONFIG_SYS_PROMPT V_PROMPT 243 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 244 /* Print Buffer Size */ 245 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 246 sizeof(CONFIG_SYS_PROMPT) + 16) 247 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 248 /* args */ 249 /* Boot Argument Buffer Size */ 250 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 251 /* memtest works on */ 252 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 253 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 254 0x01F00000) /* 31MB */ 255 256 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 257 /* address */ 258 259 /* 260 * OMAP3 has 12 GP timers, they can be driven by the system clock 261 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 262 * This rate is divided by a local divisor. 263 */ 264 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 265 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 266 #define CONFIG_SYS_HZ 1000 267 268 /*----------------------------------------------------------------------- 269 * Stack sizes 270 * 271 * The stack sizes are set up in start.S using the settings below 272 */ 273 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 274 #ifdef CONFIG_USE_IRQ 275 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 276 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 277 #endif 278 279 /*----------------------------------------------------------------------- 280 * Physical Memory Map 281 */ 282 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 283 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 284 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 285 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 286 287 /* SDRAM Bank Allocation method */ 288 #define SDRC_R_B_C 1 289 290 /*----------------------------------------------------------------------- 291 * FLASH and environment organization 292 */ 293 294 /* **** PISMO SUPPORT *** */ 295 296 /* Configure the PISMO */ 297 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 298 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 299 300 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 301 /* on one chip */ 302 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 303 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 304 305 #define CONFIG_SYS_FLASH_BASE boot_flash_base 306 307 /* Monitor at start of flash */ 308 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 309 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 310 311 #define CONFIG_ENV_IS_IN_ONENAND 1 312 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 313 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 314 315 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 316 #define CONFIG_ENV_OFFSET boot_flash_off 317 #define CONFIG_ENV_ADDR boot_flash_env_addr 318 319 /*----------------------------------------------------------------------- 320 * CFI FLASH driver setup 321 */ 322 /* timeout values are in ticks */ 323 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 324 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 325 326 /* Flash banks JFFS2 should use */ 327 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 328 CONFIG_SYS_MAX_NAND_DEVICE) 329 #define CONFIG_SYS_JFFS2_MEM_NAND 330 /* use flash_info[2] */ 331 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 332 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 333 334 #ifndef __ASSEMBLY__ 335 extern struct gpmc *gpmc_cfg; 336 extern unsigned int boot_flash_base; 337 extern volatile unsigned int boot_flash_env_addr; 338 extern unsigned int boot_flash_off; 339 extern unsigned int boot_flash_sec; 340 extern unsigned int boot_flash_type; 341 #endif 342 343 /*---------------------------------------------------------------------------- 344 * SMSC9115 Ethernet from SMSC9118 family 345 *---------------------------------------------------------------------------- 346 */ 347 #if defined(CONFIG_CMD_NET) 348 349 #define CONFIG_NET_MULTI 350 #define CONFIG_SMC911X 351 #define CONFIG_SMC911X_32_BIT 352 #define CONFIG_SMC911X_BASE 0x2C000000 353 354 #endif /* (CONFIG_CMD_NET) */ 355 356 /* 357 * BOOTP fields 358 */ 359 360 #define CONFIG_BOOTP_SUBNETMASK 0x00000001 361 #define CONFIG_BOOTP_GATEWAY 0x00000002 362 #define CONFIG_BOOTP_HOSTNAME 0x00000004 363 #define CONFIG_BOOTP_BOOTPATH 0x00000010 364 365 #endif /* __CONFIG_H */ 366