1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * Configuration settings for the TI OMAP3530 Beagle board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 */ 34 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 35 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 36 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ 37 38 #define CONFIG_SDRC /* The chip has SDRC controller */ 39 40 #include <asm/arch/cpu.h> /* get chip and board defs */ 41 #include <asm/arch/omap3.h> 42 43 /* 44 * Display CPU and Board information 45 */ 46 #define CONFIG_DISPLAY_CPUINFO 1 47 #define CONFIG_DISPLAY_BOARDINFO 1 48 49 /* Clock Defines */ 50 #define V_OSCK 26000000 /* Clock output from T2 */ 51 #define V_SCLK (V_OSCK >> 1) 52 53 #undef CONFIG_USE_IRQ /* no support for IRQs */ 54 #define CONFIG_MISC_INIT_R 55 56 #define CONFIG_OF_LIBFDT 1 57 58 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 59 #define CONFIG_SETUP_MEMORY_TAGS 1 60 #define CONFIG_INITRD_TAG 1 61 #define CONFIG_REVISION_TAG 1 62 63 /* 64 * Size of malloc() pool 65 */ 66 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 67 /* Sector */ 68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 69 70 /* 71 * Hardware drivers 72 */ 73 74 /* 75 * NS16550 Configuration 76 */ 77 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 78 79 #define CONFIG_SYS_NS16550 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 83 84 /* 85 * select serial console configuration 86 */ 87 #define CONFIG_CONS_INDEX 3 88 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 89 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ 90 91 /* allow to overwrite serial and ethaddr */ 92 #define CONFIG_ENV_OVERWRITE 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 95 115200} 96 #define CONFIG_GENERIC_MMC 1 97 #define CONFIG_MMC 1 98 #define CONFIG_OMAP_HSMMC 1 99 #define CONFIG_DOS_PARTITION 1 100 101 /* Status LED */ 102 #define CONFIG_STATUS_LED 1 103 #define CONFIG_BOARD_SPECIFIC_LED 1 104 #define STATUS_LED_BIT 0x01 105 #define STATUS_LED_STATE STATUS_LED_ON 106 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 107 #define STATUS_LED_BIT1 0x02 108 #define STATUS_LED_STATE1 STATUS_LED_ON 109 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 110 #define STATUS_LED_BOOT STATUS_LED_BIT 111 #define STATUS_LED_GREEN STATUS_LED_BIT1 112 113 /* DDR - I use Micron DDR */ 114 #define CONFIG_OMAP3_MICRON_DDR 1 115 116 /* Enable Multi Bus support for I2C */ 117 #define CONFIG_I2C_MULTI_BUS 1 118 119 /* Probe all devices */ 120 #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} 121 122 /* USB */ 123 #define CONFIG_MUSB_UDC 1 124 #define CONFIG_USB_OMAP3 1 125 #define CONFIG_TWL4030_USB 1 126 127 /* USB device configuration */ 128 #define CONFIG_USB_DEVICE 1 129 #define CONFIG_USB_TTY 1 130 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 131 132 /* USB EHCI */ 133 #define CONFIG_CMD_USB 134 #define CONFIG_USB_EHCI 135 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 136 #define CONFIG_USB_HOST_ETHER 137 #define CONFIG_USB_ETHER_SMSC95XX 138 #define CONFIG_USB_ETHER_ASIX 139 140 141 /* commands to include */ 142 #include <config_cmd_default.h> 143 144 #define CONFIG_CMD_CACHE 145 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 146 #define CONFIG_CMD_FAT /* FAT support */ 147 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 148 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 149 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 150 #define MTDIDS_DEFAULT "nand0=nand" 151 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 152 "1920k(u-boot),128k(u-boot-env),"\ 153 "4m(kernel),-(fs)" 154 155 #define CONFIG_CMD_I2C /* I2C serial bus support */ 156 #define CONFIG_CMD_MMC /* MMC support */ 157 #define CONFIG_USB_STORAGE /* USB storage support */ 158 #define CONFIG_CMD_NAND /* NAND support */ 159 #define CONFIG_CMD_LED /* LED support */ 160 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 161 #define CONFIG_CMD_NFS /* NFS support */ 162 #define CONFIG_CMD_PING 163 #define CONFIG_CMD_DHCP 164 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ 165 166 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 167 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 168 #undef CONFIG_CMD_IMI /* iminfo */ 169 #undef CONFIG_CMD_IMLS /* List all found images */ 170 171 #define CONFIG_SYS_NO_FLASH 172 #define CONFIG_HARD_I2C 1 173 #define CONFIG_SYS_I2C_SPEED 100000 174 #define CONFIG_SYS_I2C_SLAVE 1 175 #define CONFIG_SYS_I2C_BUS 0 176 #define CONFIG_SYS_I2C_BUS_SELECT 1 177 #define CONFIG_I2C_MULTI_BUS 1 178 #define CONFIG_DRIVER_OMAP34XX_I2C 1 179 #define CONFIG_VIDEO_OMAP3 /* DSS Support */ 180 181 /* 182 * TWL4030 183 */ 184 #define CONFIG_TWL4030_POWER 1 185 #define CONFIG_TWL4030_LED 1 186 187 /* 188 * Board NAND Info. 189 */ 190 #define CONFIG_SYS_NAND_QUIET_TEST 1 191 #define CONFIG_NAND_OMAP_GPMC 192 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 193 /* to access nand */ 194 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 195 /* to access nand at */ 196 /* CS0 */ 197 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 198 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 200 /* devices */ 201 #define CONFIG_JFFS2_NAND 202 /* nand device jffs2 lives on */ 203 #define CONFIG_JFFS2_DEV "nand0" 204 /* start of jffs2 partition */ 205 #define CONFIG_JFFS2_PART_OFFSET 0x680000 206 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 207 /* partition */ 208 209 /* Environment information */ 210 #define CONFIG_BOOTDELAY 2 211 212 #define CONFIG_EXTRA_ENV_SETTINGS \ 213 "loadaddr=0x80200000\0" \ 214 "rdaddr=0x81000000\0" \ 215 "usbtty=cdc_acm\0" \ 216 "bootfile=uImage.beagle\0" \ 217 "console=ttyO2,115200n8\0" \ 218 "mpurate=auto\0" \ 219 "buddy=none "\ 220 "optargs=\0" \ 221 "camera=none\0" \ 222 "vram=12M\0" \ 223 "dvimode=640x480MR-16@60\0" \ 224 "defaultdisplay=dvi\0" \ 225 "mmcdev=0\0" \ 226 "mmcroot=/dev/mmcblk0p2 rw\0" \ 227 "mmcrootfstype=ext3 rootwait\0" \ 228 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 229 "nandrootfstype=ubifs\0" \ 230 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ 231 "ramrootfstype=ext2\0" \ 232 "mmcargs=setenv bootargs console=${console} " \ 233 "${optargs} " \ 234 "mpurate=${mpurate} " \ 235 "buddy=${buddy} "\ 236 "camera=${camera} "\ 237 "vram=${vram} " \ 238 "omapfb.mode=dvi:${dvimode} " \ 239 "omapdss.def_disp=${defaultdisplay} " \ 240 "root=${mmcroot} " \ 241 "rootfstype=${mmcrootfstype}\0" \ 242 "nandargs=setenv bootargs console=${console} " \ 243 "${optargs} " \ 244 "mpurate=${mpurate} " \ 245 "buddy=${buddy} "\ 246 "camera=${camera} "\ 247 "vram=${vram} " \ 248 "omapfb.mode=dvi:${dvimode} " \ 249 "omapdss.def_disp=${defaultdisplay} " \ 250 "root=${nandroot} " \ 251 "rootfstype=${nandrootfstype}\0" \ 252 "bootenv=uEnv.txt\0" \ 253 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ 254 "importbootenv=echo Importing environment from mmc ...; " \ 255 "env import -t $loadaddr $filesize\0" \ 256 "ramargs=setenv bootargs console=${console} " \ 257 "${optargs} " \ 258 "mpurate=${mpurate} " \ 259 "buddy=${buddy} "\ 260 "vram=${vram} " \ 261 "omapfb.mode=dvi:${dvimode} " \ 262 "omapdss.def_disp=${defaultdisplay} " \ 263 "root=${ramroot} " \ 264 "rootfstype=${ramrootfstype}\0" \ 265 "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ 266 "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 267 "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ 268 "mmcboot=echo Booting from mmc ...; " \ 269 "run mmcargs; " \ 270 "bootm ${loadaddr}\0" \ 271 "nandboot=echo Booting from nand ...; " \ 272 "run nandargs; " \ 273 "nand read ${loadaddr} 280000 400000; " \ 274 "bootm ${loadaddr}\0" \ 275 "ramboot=echo Booting from ramdisk ...; " \ 276 "run ramargs; " \ 277 "bootm ${loadaddr}\0" \ 278 279 #define CONFIG_BOOTCOMMAND \ 280 "if mmc rescan ${mmcdev}; then " \ 281 "if userbutton; then " \ 282 "setenv bootenv user.txt;" \ 283 "fi;" \ 284 "echo SD/MMC found on device ${mmcdev};" \ 285 "if run loadbootenv; then " \ 286 "echo Loaded environment from ${bootenv};" \ 287 "run importbootenv;" \ 288 "fi;" \ 289 "if test -n $uenvcmd; then " \ 290 "echo Running uenvcmd ...;" \ 291 "run uenvcmd;" \ 292 "fi;" \ 293 "if run loaduimage; then " \ 294 "run mmcboot;" \ 295 "fi;" \ 296 "fi;" \ 297 "run nandboot;" \ 298 299 #define CONFIG_AUTO_COMPLETE 1 300 /* 301 * Miscellaneous configurable options 302 */ 303 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 304 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 305 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 306 #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " 307 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 308 /* Print Buffer Size */ 309 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 310 sizeof(CONFIG_SYS_PROMPT) + 16) 311 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 312 /* Boot Argument Buffer Size */ 313 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 314 315 #define CONFIG_SYS_ALT_MEMTEST 1 316 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 317 /* defaults */ 318 #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */ 319 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 320 321 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 322 /* load address */ 323 324 /* 325 * OMAP3 has 12 GP timers, they can be driven by the system clock 326 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 327 * This rate is divided by a local divisor. 328 */ 329 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 330 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 331 #define CONFIG_SYS_HZ 1000 332 333 /*----------------------------------------------------------------------- 334 * Stack sizes 335 * 336 * The stack sizes are set up in start.S using the settings below 337 */ 338 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 339 340 /*----------------------------------------------------------------------- 341 * Physical Memory Map 342 */ 343 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 344 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 345 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 346 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 347 348 /*----------------------------------------------------------------------- 349 * FLASH and environment organization 350 */ 351 352 /* **** PISMO SUPPORT *** */ 353 354 /* Configure the PISMO */ 355 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 356 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 357 358 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 359 360 #if defined(CONFIG_CMD_NAND) 361 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 362 #endif 363 364 /* Monitor at start of flash */ 365 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 366 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 367 368 #define CONFIG_ENV_IS_IN_NAND 1 369 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 370 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 371 372 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 373 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 374 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 375 376 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 377 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 378 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 379 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 380 CONFIG_SYS_INIT_RAM_SIZE - \ 381 GENERATED_GBL_DATA_SIZE) 382 383 #define CONFIG_OMAP3_SPI 384 385 #define CONFIG_SYS_CACHELINE_SIZE 64 386 387 #endif /* __CONFIG_H */ 388