1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments. 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * Configuration settings for the TI OMAP3530 Beagle board. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 #include <asm/sizes.h> 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ 36 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 39 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ 40 41 #include <asm/arch/cpu.h> /* get chip and board defs */ 42 #include <asm/arch/omap3.h> 43 44 /* 45 * Display CPU and Board information 46 */ 47 #define CONFIG_DISPLAY_CPUINFO 1 48 #define CONFIG_DISPLAY_BOARDINFO 1 49 50 /* Clock Defines */ 51 #define V_OSCK 26000000 /* Clock output from T2 */ 52 #define V_SCLK (V_OSCK >> 1) 53 54 #undef CONFIG_USE_IRQ /* no support for IRQs */ 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 58 #define CONFIG_SETUP_MEMORY_TAGS 1 59 #define CONFIG_INITRD_TAG 1 60 #define CONFIG_REVISION_TAG 1 61 62 /* 63 * Size of malloc() pool 64 */ 65 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ 66 /* Sector */ 67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 68 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 69 /* initial data */ 70 71 /* 72 * Hardware drivers 73 */ 74 75 /* 76 * NS16550 Configuration 77 */ 78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 79 80 #define CONFIG_SYS_NS16550 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 84 85 /* 86 * select serial console configuration 87 */ 88 #define CONFIG_CONS_INDEX 3 89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 90 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ 91 92 /* allow to overwrite serial and ethaddr */ 93 #define CONFIG_ENV_OVERWRITE 94 #define CONFIG_BAUDRATE 115200 95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 96 115200} 97 #define CONFIG_MMC 1 98 #define CONFIG_OMAP3_MMC 1 99 #define CONFIG_DOS_PARTITION 1 100 101 /* commands to include */ 102 #include <config_cmd_default.h> 103 104 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 105 #define CONFIG_CMD_FAT /* FAT support */ 106 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 107 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 108 #define MTDIDS_DEFAULT "nand0=nand" 109 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 110 "1920k(u-boot),128k(u-boot-env),"\ 111 "4m(kernel),-(fs)" 112 113 #define CONFIG_CMD_I2C /* I2C serial bus support */ 114 #define CONFIG_CMD_MMC /* MMC support */ 115 #define CONFIG_CMD_NAND /* NAND support */ 116 117 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 118 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 119 #undef CONFIG_CMD_IMI /* iminfo */ 120 #undef CONFIG_CMD_IMLS /* List all found images */ 121 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 122 #undef CONFIG_CMD_NFS /* NFS support */ 123 124 #define CONFIG_SYS_NO_FLASH 125 #define CONFIG_SYS_I2C_SPEED 100000 126 #define CONFIG_SYS_I2C_SLAVE 1 127 #define CONFIG_SYS_I2C_BUS 0 128 #define CONFIG_SYS_I2C_BUS_SELECT 1 129 #define CONFIG_DRIVER_OMAP34XX_I2C 1 130 131 /* 132 * Board NAND Info. 133 */ 134 #define CONFIG_NAND_OMAP_GPMC 135 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 136 /* to access nand */ 137 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 138 /* to access nand at */ 139 /* CS0 */ 140 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 141 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 143 /* devices */ 144 #define SECTORSIZE 512 145 146 #define NAND_ALLOW_ERASE_ALL 147 #define ADDR_COLUMN 1 148 #define ADDR_PAGE 2 149 #define ADDR_COLUMN_PAGE 3 150 151 #define NAND_ChipID_UNKNOWN 0x00 152 #define NAND_MAX_FLOORS 1 153 #define NAND_MAX_CHIPS 1 154 #define NAND_NO_RB 1 155 #define CONFIG_SYS_NAND_WP 156 157 #define CONFIG_JFFS2_NAND 158 /* nand device jffs2 lives on */ 159 #define CONFIG_JFFS2_DEV "nand0" 160 /* start of jffs2 partition */ 161 #define CONFIG_JFFS2_PART_OFFSET 0x680000 162 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 163 /* partition */ 164 165 /* Environment information */ 166 #define CONFIG_BOOTDELAY 10 167 168 #define CONFIG_EXTRA_ENV_SETTINGS \ 169 "loadaddr=0x82000000\0" \ 170 "console=ttyS2,115200n8\0" \ 171 "videomode=1024x768@60,vxres=1024,vyres=768\0" \ 172 "videospec=omapfb:vram:2M,vram:4M\0" \ 173 "mmcargs=setenv bootargs console=${console} " \ 174 "video=${videospec},mode:${videomode} " \ 175 "root=/dev/mmcblk0p2 rw " \ 176 "rootfstype=ext3 rootwait\0" \ 177 "nandargs=setenv bootargs console=${console} " \ 178 "video=${videospec},mode:${videomode} " \ 179 "root=/dev/mtdblock4 rw " \ 180 "rootfstype=jffs2\0" \ 181 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 182 "bootscript=echo Running bootscript from mmc ...; " \ 183 "source ${loadaddr}\0" \ 184 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 185 "mmcboot=echo Booting from mmc ...; " \ 186 "run mmcargs; " \ 187 "bootm ${loadaddr}\0" \ 188 "nandboot=echo Booting from nand ...; " \ 189 "run nandargs; " \ 190 "nand read ${loadaddr} 280000 400000; " \ 191 "bootm ${loadaddr}\0" \ 192 193 #define CONFIG_BOOTCOMMAND \ 194 "if mmc init; then " \ 195 "if run loadbootscript; then " \ 196 "run bootscript; " \ 197 "else " \ 198 "if run loaduimage; then " \ 199 "run mmcboot; " \ 200 "else run nandboot; " \ 201 "fi; " \ 202 "fi; " \ 203 "else run nandboot; fi" 204 205 #define CONFIG_AUTO_COMPLETE 1 206 /* 207 * Miscellaneous configurable options 208 */ 209 #define V_PROMPT "OMAP3 beagleboard.org # " 210 211 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 212 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 213 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 214 #define CONFIG_SYS_PROMPT V_PROMPT 215 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 216 /* Print Buffer Size */ 217 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 218 sizeof(CONFIG_SYS_PROMPT) + 16) 219 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 220 /* Boot Argument Buffer Size */ 221 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 222 223 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 224 /* works on */ 225 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 226 0x01F00000) /* 31MB */ 227 228 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 229 /* load address */ 230 231 /* 232 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by 233 * 32KHz clk, or from external sig. This rate is divided by a local divisor. 234 */ 235 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 236 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ 237 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) 238 239 /*----------------------------------------------------------------------- 240 * Stack sizes 241 * 242 * The stack sizes are set up in start.S using the settings below 243 */ 244 #define CONFIG_STACKSIZE SZ_128K /* regular stack */ 245 #ifdef CONFIG_USE_IRQ 246 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ 247 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ 248 #endif 249 250 /*----------------------------------------------------------------------- 251 * Physical Memory Map 252 */ 253 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 254 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 255 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ 256 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 257 258 /* SDRAM Bank Allocation method */ 259 #define SDRC_R_B_C 1 260 261 /*----------------------------------------------------------------------- 262 * FLASH and environment organization 263 */ 264 265 /* **** PISMO SUPPORT *** */ 266 267 /* Configure the PISMO */ 268 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 269 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 270 271 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 272 /* one chip */ 273 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 274 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ 275 276 #define CONFIG_SYS_FLASH_BASE boot_flash_base 277 278 /* Monitor at start of flash */ 279 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 280 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 281 282 #define CONFIG_ENV_IS_IN_NAND 1 283 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 284 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 285 286 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 287 #define CONFIG_ENV_OFFSET boot_flash_off 288 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 289 290 /*----------------------------------------------------------------------- 291 * CFI FLASH driver setup 292 */ 293 /* timeout values are in ticks */ 294 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 295 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 296 297 /* Flash banks JFFS2 should use */ 298 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 299 CONFIG_SYS_MAX_NAND_DEVICE) 300 #define CONFIG_SYS_JFFS2_MEM_NAND 301 /* use flash_info[2] */ 302 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 303 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 304 305 #ifndef __ASSEMBLY__ 306 extern gpmc_csx_t *nand_cs_base; 307 extern gpmc_t *gpmc_cfg_base; 308 extern unsigned int boot_flash_base; 309 extern volatile unsigned int boot_flash_env_addr; 310 extern unsigned int boot_flash_off; 311 extern unsigned int boot_flash_sec; 312 extern unsigned int boot_flash_type; 313 #endif 314 315 316 #define WRITE_NAND_COMMAND(d, adr)\ 317 writel(d, &nand_cs_base->nand_cmd) 318 #define WRITE_NAND_ADDRESS(d, adr)\ 319 writel(d, &nand_cs_base->nand_adr) 320 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) 321 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat) 322 323 /* Other NAND Access APIs */ 324 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ 325 while (0) 326 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ 327 while (0) 328 #define NAND_DISABLE_CE(nand) 329 #define NAND_ENABLE_CE(nand) 330 #define NAND_WAIT_READY(nand) udelay(10) 331 332 #endif /* __CONFIG_H */ 333