1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX7D SABRESD board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MX7D_SABRESD_CONFIG_H 10 #define __MX7D_SABRESD_CONFIG_H 11 12 #include "mx7_common.h" 13 14 #define CONFIG_DBG_MONITOR 15 #define PHYS_SDRAM_SIZE SZ_1G 16 17 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR 18 19 #define CONFIG_BOARD_EARLY_INIT_F 20 #define CONFIG_BOARD_LATE_INIT 21 22 /* Uncomment to enable secure boot support */ 23 /* #define CONFIG_SECURE_BOOT */ 24 #define CONFIG_CSF_SIZE 0x4000 25 26 /* Network */ 27 #define CONFIG_CMD_MII 28 #define CONFIG_FEC_MXC 29 #define CONFIG_MII 30 #define CONFIG_FEC_XCV_TYPE RGMII 31 #define CONFIG_ETHPRIME "FEC" 32 #define CONFIG_FEC_MXC_PHYADDR 0 33 34 #define CONFIG_PHYLIB 35 #define CONFIG_PHY_BROADCOM 36 /* ENET1 */ 37 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR 38 39 /* MMC Config*/ 40 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 41 42 /* PMIC */ 43 #define CONFIG_POWER 44 #define CONFIG_POWER_I2C 45 #define CONFIG_POWER_PFUZE3000 46 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 47 48 #undef CONFIG_BOOTM_NETBSD 49 #undef CONFIG_BOOTM_PLAN9 50 #undef CONFIG_BOOTM_RTEMS 51 52 #undef CONFIG_CMD_EXPORTENV 53 #undef CONFIG_CMD_IMPORTENV 54 55 /* I2C configs */ 56 #define CONFIG_CMD_I2C 57 #define CONFIG_SYS_I2C 58 #define CONFIG_SYS_I2C_MXC 59 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 60 #define CONFIG_SYS_I2C_SPEED 100000 61 62 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 63 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 64 65 #ifdef CONFIG_IMX_BOOTAUX 66 /* Set to QSPI1 A flash at default */ 67 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 68 #define CONFIG_CMD_SETEXPR 69 70 #define UPDATE_M4_ENV \ 71 "m4image=m4_qspi.bin\0" \ 72 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ 73 "update_m4_from_sd=" \ 74 "if sf probe 0:0; then " \ 75 "if run loadm4image; then " \ 76 "setexpr fw_sz ${filesize} + 0xffff; " \ 77 "setexpr fw_sz ${fw_sz} / 0x10000; " \ 78 "setexpr fw_sz ${fw_sz} * 0x10000; " \ 79 "sf erase 0x0 ${fw_sz}; " \ 80 "sf write ${loadaddr} 0x0 ${filesize}; " \ 81 "fi; " \ 82 "fi\0" \ 83 "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" 84 #else 85 #define UPDATE_M4_ENV "" 86 #endif 87 88 #define CONFIG_MFG_ENV_SETTINGS \ 89 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ 90 "rdinit=/linuxrc " \ 91 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ 92 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ 93 "g_mass_storage.iSerialNumber=\"\" "\ 94 "clk_ignore_unused "\ 95 "\0" \ 96 "initrd_addr=0x83800000\0" \ 97 "initrd_high=0xffffffff\0" \ 98 "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ 99 100 #define CONFIG_DFU_ENV_SETTINGS \ 101 "dfu_alt_info=image raw 0 0x800000;"\ 102 "u-boot raw 0 0x4000;"\ 103 "bootimg part 0 1;"\ 104 "rootfs part 0 2\0" \ 105 106 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 UPDATE_M4_ENV \ 108 CONFIG_MFG_ENV_SETTINGS \ 109 CONFIG_DFU_ENV_SETTINGS \ 110 "script=boot.scr\0" \ 111 "image=zImage\0" \ 112 "console=ttymxc0\0" \ 113 "fdt_high=0xffffffff\0" \ 114 "initrd_high=0xffffffff\0" \ 115 "fdt_file=imx7d-sdb.dtb\0" \ 116 "fdt_addr=0x83000000\0" \ 117 "boot_fdt=try\0" \ 118 "ip_dyn=yes\0" \ 119 "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ 120 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ 121 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ 122 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 123 "mmcautodetect=yes\0" \ 124 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 125 "root=${mmcroot}\0" \ 126 "loadbootscript=" \ 127 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 128 "bootscript=echo Running bootscript from mmc ...; " \ 129 "source\0" \ 130 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 131 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 132 "mmcboot=echo Booting from mmc ...; " \ 133 "run mmcargs; " \ 134 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 135 "if run loadfdt; then " \ 136 "bootz ${loadaddr} - ${fdt_addr}; " \ 137 "else " \ 138 "if test ${boot_fdt} = try; then " \ 139 "bootz; " \ 140 "else " \ 141 "echo WARN: Cannot load the DT; " \ 142 "fi; " \ 143 "fi; " \ 144 "else " \ 145 "bootz; " \ 146 "fi;\0" \ 147 "netargs=setenv bootargs console=${console},${baudrate} " \ 148 "root=/dev/nfs " \ 149 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 150 "netboot=echo Booting from net ...; " \ 151 "run netargs; " \ 152 "if test ${ip_dyn} = yes; then " \ 153 "setenv get_cmd dhcp; " \ 154 "else " \ 155 "setenv get_cmd tftp; " \ 156 "fi; " \ 157 "${get_cmd} ${image}; " \ 158 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 159 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 160 "bootz ${loadaddr} - ${fdt_addr}; " \ 161 "else " \ 162 "if test ${boot_fdt} = try; then " \ 163 "bootz; " \ 164 "else " \ 165 "echo WARN: Cannot load the DT; " \ 166 "fi; " \ 167 "fi; " \ 168 "else " \ 169 "bootz; " \ 170 "fi;\0" 171 172 #define CONFIG_BOOTCOMMAND \ 173 "mmc dev ${mmcdev};" \ 174 "mmc dev ${mmcdev}; if mmc rescan; then " \ 175 "if run loadbootscript; then " \ 176 "run bootscript; " \ 177 "else " \ 178 "if run loadimage; then " \ 179 "run mmcboot; " \ 180 "else run netboot; " \ 181 "fi; " \ 182 "fi; " \ 183 "else run netboot; fi" 184 185 #define CONFIG_CMD_MEMTEST 186 #define CONFIG_SYS_MEMTEST_START 0x80000000 187 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) 188 189 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 190 #define CONFIG_SYS_HZ 1000 191 192 #define CONFIG_STACKSIZE SZ_128K 193 194 /* Physical Memory Map */ 195 #define CONFIG_NR_DRAM_BANKS 1 196 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 197 198 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 199 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 200 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 201 202 #define CONFIG_SYS_INIT_SP_OFFSET \ 203 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 204 #define CONFIG_SYS_INIT_SP_ADDR \ 205 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 206 207 /* FLASH and environment organization */ 208 #define CONFIG_SYS_NO_FLASH 209 #define CONFIG_ENV_SIZE SZ_8K 210 #define CONFIG_ENV_IS_IN_MMC 211 212 /* 213 * If want to use nand, define CONFIG_NAND_MXS and rework board 214 * to support nand, since emmc has pin conflicts with nand 215 */ 216 #ifdef CONFIG_NAND_MXS 217 #define CONFIG_CMD_NAND 218 #define CONFIG_CMD_NAND_TRIMFFS 219 220 /* NAND stuff */ 221 #define CONFIG_SYS_MAX_NAND_DEVICE 1 222 #define CONFIG_SYS_NAND_BASE 0x40000000 223 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 224 #define CONFIG_SYS_NAND_ONFI_DETECTION 225 226 /* DMA stuff, needed for GPMI/MXS NAND support */ 227 #define CONFIG_APBH_DMA 228 #define CONFIG_APBH_DMA_BURST 229 #define CONFIG_APBH_DMA_BURST8 230 #endif 231 232 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 233 #ifdef CONFIG_NAND_MXS 234 #define CONFIG_SYS_FSL_USDHC_NUM 1 235 #else 236 #define CONFIG_SYS_FSL_USDHC_NUM 2 237 #endif 238 239 #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ 240 #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 241 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ 242 243 /* USB Configs */ 244 #define CONFIG_CMD_USB 245 #define CONFIG_USB_EHCI 246 #define CONFIG_USB_EHCI_MX7 247 #define CONFIG_USB_STORAGE 248 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 249 #define CONFIG_USB_HOST_ETHER 250 #define CONFIG_USB_ETHER_ASIX 251 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 252 #define CONFIG_MXC_USB_FLAGS 0 253 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 254 255 #define CONFIG_IMX_THERMAL 256 257 #define CONFIG_CI_UDC 258 #define CONFIG_USBD_HS 259 #define CONFIG_USB_GADGET_DUALSPEED 260 261 #define CONFIG_USB_GADGET 262 #define CONFIG_CMD_USB_MASS_STORAGE 263 #define CONFIG_USB_FUNCTION_MASS_STORAGE 264 #define CONFIG_USB_GADGET_DOWNLOAD 265 #define CONFIG_USB_GADGET_VBUS_DRAW 2 266 267 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 268 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 269 #define CONFIG_G_DNL_MANUFACTURER "FSL" 270 271 /* USB Device Firmware Update support */ 272 #define CONFIG_CMD_DFU 273 #define CONFIG_USB_FUNCTION_DFU 274 #define CONFIG_DFU_MMC 275 #define CONFIG_DFU_RAM 276 277 #define CONFIG_VIDEO 278 #ifdef CONFIG_VIDEO 279 #define CONFIG_CFB_CONSOLE 280 #define CONFIG_VIDEO_MXS 281 #define CONFIG_VIDEO_LOGO 282 #define CONFIG_VIDEO_SW_CURSOR 283 #define CONFIG_VGA_AS_SINGLE_DEVICE 284 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 285 #define CONFIG_SPLASH_SCREEN 286 #define CONFIG_SPLASH_SCREEN_ALIGN 287 #define CONFIG_CMD_BMP 288 #define CONFIG_BMP_16BPP 289 #define CONFIG_VIDEO_BMP_RLE8 290 #define CONFIG_VIDEO_BMP_LOGO 291 #endif 292 293 #ifdef CONFIG_FSL_QSPI 294 #define CONFIG_CMD_SF 295 #define CONFIG_SPI_FLASH 296 #define CONFIG_SPI_FLASH_MACRONIX 297 #define CONFIG_SPI_FLASH_BAR 298 #define CONFIG_SF_DEFAULT_BUS 0 299 #define CONFIG_SF_DEFAULT_CS 0 300 #define CONFIG_SF_DEFAULT_SPEED 40000000 301 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 302 #define FSL_QSPI_FLASH_NUM 1 303 #define FSL_QSPI_FLASH_SIZE SZ_64M 304 #define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR 305 #define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR 306 #endif 307 308 #endif /* __CONFIG_H */ 309