1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6SX Sabresd board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "mx6_common.h" 14 15 #ifdef CONFIG_SPL 16 #define CONFIG_SPL_LIBCOMMON_SUPPORT 17 #define CONFIG_SPL_MMC_SUPPORT 18 #include "imx6_spl.h" 19 #endif 20 21 /* Size of malloc() pool */ 22 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) 23 24 #define CONFIG_BOARD_EARLY_INIT_F 25 26 #define CONFIG_MXC_UART 27 #define CONFIG_MXC_UART_BASE UART1_BASE 28 29 #ifdef CONFIG_IMX_BOOTAUX 30 /* Set to QSPI2 B flash at default */ 31 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 32 33 #define UPDATE_M4_ENV \ 34 "m4image=m4_qspi.bin\0" \ 35 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ 36 "update_m4_from_sd=" \ 37 "if sf probe 1:0; then " \ 38 "if run loadm4image; then " \ 39 "setexpr fw_sz ${filesize} + 0xffff; " \ 40 "setexpr fw_sz ${fw_sz} / 0x10000; " \ 41 "setexpr fw_sz ${fw_sz} * 0x10000; " \ 42 "sf erase 0x0 ${fw_sz}; " \ 43 "sf write ${loadaddr} 0x0 ${filesize}; " \ 44 "fi; " \ 45 "fi\0" \ 46 "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" 47 #else 48 #define UPDATE_M4_ENV "" 49 #endif 50 51 #define CONFIG_EXTRA_ENV_SETTINGS \ 52 UPDATE_M4_ENV \ 53 "script=boot.scr\0" \ 54 "image=zImage\0" \ 55 "console=ttymxc0\0" \ 56 "fdt_high=0xffffffff\0" \ 57 "initrd_high=0xffffffff\0" \ 58 "fdt_file=imx6sx-sdb.dtb\0" \ 59 "fdt_addr=0x88000000\0" \ 60 "boot_fdt=try\0" \ 61 "ip_dyn=yes\0" \ 62 "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ 63 "mmcdev=2\0" \ 64 "mmcpart=1\0" \ 65 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 66 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 67 "root=${mmcroot}\0" \ 68 "loadbootscript=" \ 69 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 70 "bootscript=echo Running bootscript from mmc ...; " \ 71 "source\0" \ 72 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 73 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 74 "mmcboot=echo Booting from mmc ...; " \ 75 "run mmcargs; " \ 76 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 77 "if run loadfdt; then " \ 78 "bootz ${loadaddr} - ${fdt_addr}; " \ 79 "else " \ 80 "if test ${boot_fdt} = try; then " \ 81 "bootz; " \ 82 "else " \ 83 "echo WARN: Cannot load the DT; " \ 84 "fi; " \ 85 "fi; " \ 86 "else " \ 87 "bootz; " \ 88 "fi;\0" \ 89 "netargs=setenv bootargs console=${console},${baudrate} " \ 90 "root=/dev/nfs " \ 91 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 92 "netboot=echo Booting from net ...; " \ 93 "run netargs; " \ 94 "if test ${ip_dyn} = yes; then " \ 95 "setenv get_cmd dhcp; " \ 96 "else " \ 97 "setenv get_cmd tftp; " \ 98 "fi; " \ 99 "${get_cmd} ${image}; " \ 100 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 101 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 102 "bootz ${loadaddr} - ${fdt_addr}; " \ 103 "else " \ 104 "if test ${boot_fdt} = try; then " \ 105 "bootz; " \ 106 "else " \ 107 "echo WARN: Cannot load the DT; " \ 108 "fi; " \ 109 "fi; " \ 110 "else " \ 111 "bootz; " \ 112 "fi;\0" 113 114 #define CONFIG_BOOTCOMMAND \ 115 "mmc dev ${mmcdev};" \ 116 "mmc dev ${mmcdev}; if mmc rescan; then " \ 117 "if run loadbootscript; then " \ 118 "run bootscript; " \ 119 "else " \ 120 "if run loadimage; then " \ 121 "run mmcboot; " \ 122 "else run netboot; " \ 123 "fi; " \ 124 "fi; " \ 125 "else run netboot; fi" 126 127 /* Miscellaneous configurable options */ 128 #define CONFIG_SYS_MEMTEST_START 0x80000000 129 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) 130 131 #define CONFIG_STACKSIZE SZ_128K 132 133 /* Physical Memory Map */ 134 #define CONFIG_NR_DRAM_BANKS 1 135 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 136 #define PHYS_SDRAM_SIZE SZ_1G 137 138 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 139 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 140 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 141 142 #define CONFIG_SYS_INIT_SP_OFFSET \ 143 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 144 #define CONFIG_SYS_INIT_SP_ADDR \ 145 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 146 147 /* MMC Configuration */ 148 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR 149 150 /* I2C Configs */ 151 #define CONFIG_SYS_I2C 152 #define CONFIG_SYS_I2C_MXC 153 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 154 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 155 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 156 #define CONFIG_SYS_I2C_SPEED 100000 157 158 /* PMIC */ 159 #define CONFIG_POWER 160 #define CONFIG_POWER_I2C 161 #define CONFIG_POWER_PFUZE100 162 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 163 164 /* Network */ 165 #define CONFIG_CMD_MII 166 #define CONFIG_FEC_MXC 167 #define CONFIG_MII 168 169 #define IMX_FEC_BASE ENET_BASE_ADDR 170 #define CONFIG_FEC_MXC_PHYADDR 0x1 171 172 #define CONFIG_FEC_XCV_TYPE RGMII 173 #define CONFIG_ETHPRIME "FEC" 174 175 #define CONFIG_PHYLIB 176 #define CONFIG_PHY_ATHEROS 177 178 179 #ifdef CONFIG_CMD_USB 180 #define CONFIG_USB_EHCI 181 #define CONFIG_USB_EHCI_MX6 182 #define CONFIG_USB_STORAGE 183 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 184 #define CONFIG_USB_HOST_ETHER 185 #define CONFIG_USB_ETHER_ASIX 186 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 187 #define CONFIG_MXC_USB_FLAGS 0 188 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 189 #endif 190 191 #define CONFIG_CMD_PCI 192 #ifdef CONFIG_CMD_PCI 193 #define CONFIG_PCI 194 #define CONFIG_PCI_PNP 195 #define CONFIG_PCI_SCAN_SHOW 196 #define CONFIG_PCIE_IMX 197 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) 198 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) 199 #endif 200 201 #define CONFIG_IMX_THERMAL 202 203 204 205 #ifdef CONFIG_FSL_QSPI 206 #define CONFIG_SYS_FSL_QSPI_LE 207 #define CONFIG_SYS_FSL_QSPI_AHB 208 #ifdef CONFIG_MX6SX_SABRESD_REVA 209 #define FSL_QSPI_FLASH_SIZE SZ_16M 210 #else 211 #define FSL_QSPI_FLASH_SIZE SZ_32M 212 #endif 213 #define FSL_QSPI_FLASH_NUM 2 214 #endif 215 216 #ifndef CONFIG_SPL_BUILD 217 #define CONFIG_VIDEO 218 #ifdef CONFIG_VIDEO 219 #define CONFIG_CFB_CONSOLE 220 #define CONFIG_VIDEO_MXS 221 #define CONFIG_VIDEO_LOGO 222 #define CONFIG_VIDEO_SW_CURSOR 223 #define CONFIG_VGA_AS_SINGLE_DEVICE 224 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 225 #define CONFIG_SPLASH_SCREEN 226 #define CONFIG_SPLASH_SCREEN_ALIGN 227 #define CONFIG_CMD_BMP 228 #define CONFIG_BMP_16BPP 229 #define CONFIG_VIDEO_BMP_RLE8 230 #define CONFIG_VIDEO_BMP_LOGO 231 #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR 232 #endif 233 #endif 234 235 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 236 #define CONFIG_ENV_SIZE SZ_8K 237 #define CONFIG_ENV_IS_IN_MMC 238 239 #define CONFIG_SYS_FSL_USDHC_NUM 3 240 #if defined(CONFIG_ENV_IS_IN_MMC) 241 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ 242 #endif 243 244 #endif /* __CONFIG_H */ 245