1c1747970SPierre Aubert /* 2c1747970SPierre Aubert * Copyright (C) 2012 Freescale Semiconductor, Inc. 3c1747970SPierre Aubert * 4c1747970SPierre Aubert * Configuration settings for the Freescale i.MX6Q SabreSD board. 5c1747970SPierre Aubert * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7c1747970SPierre Aubert */ 8c1747970SPierre Aubert 9c1747970SPierre Aubert #ifndef __MX6QSABRESD_CONFIG_H 10c1747970SPierre Aubert #define __MX6QSABRESD_CONFIG_H 11c1747970SPierre Aubert 121558200aSJohn Tobias #ifdef CONFIG_SPL 131558200aSJohn Tobias #include "imx6_spl.h" 141558200aSJohn Tobias #endif 151558200aSJohn Tobias 16c1747970SPierre Aubert #define CONFIG_MACH_TYPE 3980 17c1747970SPierre Aubert #define CONFIG_MXC_UART_BASE UART1_BASE 1812ca05a3SSimon Glass #define CONSOLE_DEV "ttymxc0" 19c1747970SPierre Aubert #define CONFIG_MMCROOT "/dev/mmcblk1p2" 20c1747970SPierre Aubert 2103ce3302SOtavio Salvador #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 2203ce3302SOtavio Salvador 23c1747970SPierre Aubert #include "mx6sabre_common.h" 24c1747970SPierre Aubert 25d96796caSDiego Dorta /* Falcon Mode */ 26*dec30306STom Rini #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 27*dec30306STom Rini #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 28d96796caSDiego Dorta #define CONFIG_CMD_SPL 29d96796caSDiego Dorta #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 30d96796caSDiego Dorta #define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) 31d96796caSDiego Dorta 32d96796caSDiego Dorta /* Falcon Mode - MMC support: args@1MB kernel@2MB */ 33d96796caSDiego Dorta #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ 34d96796caSDiego Dorta #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) 35d96796caSDiego Dorta #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ 36d96796caSDiego Dorta 37c1747970SPierre Aubert #define CONFIG_SYS_FSL_USDHC_NUM 3 38c1747970SPierre Aubert #if defined(CONFIG_ENV_IS_IN_MMC) 39c1747970SPierre Aubert #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ 40c1747970SPierre Aubert #endif 41c1747970SPierre Aubert 42e919aa23SMarek Vasut #define CONFIG_CMD_PCI 43e919aa23SMarek Vasut #ifdef CONFIG_CMD_PCI 44e919aa23SMarek Vasut #define CONFIG_PCI_SCAN_SHOW 45e919aa23SMarek Vasut #define CONFIG_PCIE_IMX 46e919aa23SMarek Vasut #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 47e919aa23SMarek Vasut #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) 48e919aa23SMarek Vasut #endif 49e919aa23SMarek Vasut 5066ca09fcSFabio Estevam /* I2C Configs */ 5166ca09fcSFabio Estevam #define CONFIG_SYS_I2C 5266ca09fcSFabio Estevam #define CONFIG_SYS_I2C_MXC 5303544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 5403544c66SAlbert ARIBAUD \\(3ADEV\\) #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 55f8cb101eSYork Sun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 5666ca09fcSFabio Estevam #define CONFIG_SYS_I2C_SPEED 100000 5766ca09fcSFabio Estevam 5866ca09fcSFabio Estevam /* PMIC */ 5966ca09fcSFabio Estevam #define CONFIG_POWER 6066ca09fcSFabio Estevam #define CONFIG_POWER_I2C 6166ca09fcSFabio Estevam #define CONFIG_POWER_PFUZE100 6266ca09fcSFabio Estevam #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 6366ca09fcSFabio Estevam 645a3d63c5SPeng Fan /* USB Configs */ 655a3d63c5SPeng Fan #ifdef CONFIG_CMD_USB 665a3d63c5SPeng Fan #define CONFIG_USB_EHCI 675a3d63c5SPeng Fan #define CONFIG_USB_EHCI_MX6 685a3d63c5SPeng Fan #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 695a3d63c5SPeng Fan #define CONFIG_USB_HOST_ETHER 705a3d63c5SPeng Fan #define CONFIG_USB_ETHER_ASIX 715a3d63c5SPeng Fan #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 725a3d63c5SPeng Fan #define CONFIG_MXC_USB_FLAGS 0 735a3d63c5SPeng Fan #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ 745a3d63c5SPeng Fan #endif 755a3d63c5SPeng Fan 76c1747970SPierre Aubert #endif /* __MX6QSABRESD_CONFIG_H */ 77