1*d7c11502SVanessa Maegima /* 2*d7c11502SVanessa Maegima * Copyright (C) 2012 Freescale Semiconductor, Inc. 3*d7c11502SVanessa Maegima * 4*d7c11502SVanessa Maegima * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5*d7c11502SVanessa Maegima * 6*d7c11502SVanessa Maegima * SPDX-License-Identifier: GPL-2.0+ 7*d7c11502SVanessa Maegima */ 8*d7c11502SVanessa Maegima 9*d7c11502SVanessa Maegima #ifndef __MX6SABREAUTO_CONFIG_H 10*d7c11502SVanessa Maegima #define __MX6SABREAUTO_CONFIG_H 11*d7c11502SVanessa Maegima 12*d7c11502SVanessa Maegima #ifdef CONFIG_SPL 13*d7c11502SVanessa Maegima #include "imx6_spl.h" 14*d7c11502SVanessa Maegima #endif 15*d7c11502SVanessa Maegima 16*d7c11502SVanessa Maegima #define CONFIG_MACH_TYPE 3529 17*d7c11502SVanessa Maegima #define CONFIG_MXC_UART_BASE UART4_BASE 18*d7c11502SVanessa Maegima #define CONSOLE_DEV "ttymxc3" 19*d7c11502SVanessa Maegima #define CONFIG_MMCROOT "/dev/mmcblk0p2" 20*d7c11502SVanessa Maegima 21*d7c11502SVanessa Maegima /* USB Configs */ 22*d7c11502SVanessa Maegima #define CONFIG_USB_HOST_ETHER 23*d7c11502SVanessa Maegima #define CONFIG_USB_ETHER_ASIX 24*d7c11502SVanessa Maegima #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 25*d7c11502SVanessa Maegima #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 26*d7c11502SVanessa Maegima #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 27*d7c11502SVanessa Maegima #define CONFIG_MXC_USB_FLAGS 0 28*d7c11502SVanessa Maegima 29*d7c11502SVanessa Maegima #define CONFIG_PCA953X 30*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 31*d7c11502SVanessa Maegima 32*d7c11502SVanessa Maegima #include "mx6sabre_common.h" 33*d7c11502SVanessa Maegima 34*d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 35*d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 36*d7c11502SVanessa Maegima #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 37*d7c11502SVanessa Maegima #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 38*d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 39*d7c11502SVanessa Maegima #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 40*d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 41*d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_EMPTY_INFO 42*d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 43*d7c11502SVanessa Maegima 44*d7c11502SVanessa Maegima #define CONFIG_SYS_FSL_USDHC_NUM 2 45*d7c11502SVanessa Maegima #if defined(CONFIG_ENV_IS_IN_MMC) 46*d7c11502SVanessa Maegima #define CONFIG_SYS_MMC_ENV_DEV 0 47*d7c11502SVanessa Maegima #endif 48*d7c11502SVanessa Maegima 49*d7c11502SVanessa Maegima /* I2C Configs */ 50*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C 51*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC 52*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 53*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 54*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 55*d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_SPEED 100000 56*d7c11502SVanessa Maegima 57*d7c11502SVanessa Maegima /* NAND flash command */ 58*d7c11502SVanessa Maegima #define CONFIG_CMD_NAND 59*d7c11502SVanessa Maegima #define CONFIG_CMD_NAND_TRIMFFS 60*d7c11502SVanessa Maegima 61*d7c11502SVanessa Maegima /* NAND stuff */ 62*d7c11502SVanessa Maegima #define CONFIG_NAND_MXS 63*d7c11502SVanessa Maegima #define CONFIG_SYS_MAX_NAND_DEVICE 1 64*d7c11502SVanessa Maegima #define CONFIG_SYS_NAND_BASE 0x40000000 65*d7c11502SVanessa Maegima #define CONFIG_SYS_NAND_5_ADDR_CYCLE 66*d7c11502SVanessa Maegima #define CONFIG_SYS_NAND_ONFI_DETECTION 67*d7c11502SVanessa Maegima 68*d7c11502SVanessa Maegima /* DMA stuff, needed for GPMI/MXS NAND support */ 69*d7c11502SVanessa Maegima #define CONFIG_APBH_DMA 70*d7c11502SVanessa Maegima #define CONFIG_APBH_DMA_BURST 71*d7c11502SVanessa Maegima #define CONFIG_APBH_DMA_BURST8 72*d7c11502SVanessa Maegima 73*d7c11502SVanessa Maegima /* PMIC */ 74*d7c11502SVanessa Maegima #define CONFIG_POWER 75*d7c11502SVanessa Maegima #define CONFIG_POWER_I2C 76*d7c11502SVanessa Maegima #define CONFIG_POWER_PFUZE100 77*d7c11502SVanessa Maegima #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 78*d7c11502SVanessa Maegima 79*d7c11502SVanessa Maegima #endif /* __MX6SABREAUTO_CONFIG_H */ 80