1d7c11502SVanessa Maegima /* 2d7c11502SVanessa Maegima * Copyright (C) 2012 Freescale Semiconductor, Inc. 3d7c11502SVanessa Maegima * 4d7c11502SVanessa Maegima * Configuration settings for the Freescale i.MX6Q SabreAuto board. 5d7c11502SVanessa Maegima * 6d7c11502SVanessa Maegima * SPDX-License-Identifier: GPL-2.0+ 7d7c11502SVanessa Maegima */ 8d7c11502SVanessa Maegima 9d7c11502SVanessa Maegima #ifndef __MX6SABREAUTO_CONFIG_H 10d7c11502SVanessa Maegima #define __MX6SABREAUTO_CONFIG_H 11d7c11502SVanessa Maegima 12d7c11502SVanessa Maegima #ifdef CONFIG_SPL 13d7c11502SVanessa Maegima #include "imx6_spl.h" 14d7c11502SVanessa Maegima #endif 15d7c11502SVanessa Maegima 16d7c11502SVanessa Maegima #define CONFIG_MACH_TYPE 3529 17d7c11502SVanessa Maegima #define CONFIG_MXC_UART_BASE UART4_BASE 18d7c11502SVanessa Maegima #define CONSOLE_DEV "ttymxc3" 19d7c11502SVanessa Maegima 20d7c11502SVanessa Maegima /* USB Configs */ 21d7c11502SVanessa Maegima #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 22d7c11502SVanessa Maegima #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 23d7c11502SVanessa Maegima #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 24d7c11502SVanessa Maegima #define CONFIG_MXC_USB_FLAGS 0 25d7c11502SVanessa Maegima 26d7c11502SVanessa Maegima #define CONFIG_PCA953X 27d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } 28d7c11502SVanessa Maegima 29d7c11502SVanessa Maegima #include "mx6sabre_common.h" 30d7c11502SVanessa Maegima 31*07f6ddb6SDiego Dorta /* Falcon Mode */ 32*07f6ddb6SDiego Dorta #ifdef CONFIG_SPL_OS_BOOT 33*07f6ddb6SDiego Dorta #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 34*07f6ddb6SDiego Dorta #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 35*07f6ddb6SDiego Dorta #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 36*07f6ddb6SDiego Dorta 37*07f6ddb6SDiego Dorta /* Falcon Mode - MMC support: args@1MB kernel@2MB */ 38*07f6ddb6SDiego Dorta #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ 39*07f6ddb6SDiego Dorta #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) 40*07f6ddb6SDiego Dorta #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ 41*07f6ddb6SDiego Dorta #endif 42*07f6ddb6SDiego Dorta 43ca62e5d0SFabio Estevam #ifdef CONFIG_MTD_NOR_FLASH 44d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR 45d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 46d7c11502SVanessa Maegima #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 47d7c11502SVanessa Maegima #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 48d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 49d7c11502SVanessa Maegima #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ 50d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ 51d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_EMPTY_INFO 52d7c11502SVanessa Maegima #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 53ca62e5d0SFabio Estevam #endif 54d7c11502SVanessa Maegima 55d7c11502SVanessa Maegima #define CONFIG_SYS_FSL_USDHC_NUM 2 56d7c11502SVanessa Maegima #if defined(CONFIG_ENV_IS_IN_MMC) 57d7c11502SVanessa Maegima #define CONFIG_SYS_MMC_ENV_DEV 0 58d7c11502SVanessa Maegima #endif 59d7c11502SVanessa Maegima 60d7c11502SVanessa Maegima /* I2C Configs */ 61d7c11502SVanessa Maegima #define CONFIG_SYS_I2C 62d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC 63d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 64d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 65d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 66d7c11502SVanessa Maegima #define CONFIG_SYS_I2C_SPEED 100000 67d7c11502SVanessa Maegima 68d7c11502SVanessa Maegima /* NAND stuff */ 69d7c11502SVanessa Maegima #define CONFIG_SYS_MAX_NAND_DEVICE 1 70d7c11502SVanessa Maegima #define CONFIG_SYS_NAND_BASE 0x40000000 71d7c11502SVanessa Maegima #define CONFIG_SYS_NAND_5_ADDR_CYCLE 72d7c11502SVanessa Maegima #define CONFIG_SYS_NAND_ONFI_DETECTION 73d7c11502SVanessa Maegima 74d7c11502SVanessa Maegima /* DMA stuff, needed for GPMI/MXS NAND support */ 75d7c11502SVanessa Maegima 76d7c11502SVanessa Maegima /* PMIC */ 77d7c11502SVanessa Maegima #define CONFIG_POWER 78d7c11502SVanessa Maegima #define CONFIG_POWER_I2C 79d7c11502SVanessa Maegima #define CONFIG_POWER_PFUZE100 80d7c11502SVanessa Maegima #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 81d7c11502SVanessa Maegima 82d7c11502SVanessa Maegima #endif /* __MX6SABREAUTO_CONFIG_H */ 83