xref: /rk3399_rockchip-uboot/include/configs/mx53smd.h (revision 19a9747535c105fa458d0c9929e6785cf56d1292)
1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc.
3  *
4  * Configuration settings for the MX53SMD Freescale board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_MX53
13 
14 #define CONFIG_DISPLAY_BOARDINFO
15 
16 #define CONFIG_MACH_TYPE	MACH_TYPE_MX53_SMD
17 
18 #include <asm/arch/imx-regs.h>
19 
20 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
21 #define CONFIG_SETUP_MEMORY_TAGS
22 #define CONFIG_INITRD_TAG
23 #define CONFIG_REVISION_TAG
24 
25 #define CONFIG_SYS_FSL_CLK
26 
27 /* Size of malloc() pool */
28 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
29 
30 #define CONFIG_BOARD_EARLY_INIT_F
31 #define CONFIG_MXC_GPIO
32 
33 #define CONFIG_MXC_UART
34 #define CONFIG_MXC_UART_BASE	UART1_BASE
35 
36 /* I2C Configs */
37 #define CONFIG_SYS_I2C
38 #define CONFIG_SYS_I2C_MXC
39 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
40 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
41 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
42 
43 /* MMC Configs */
44 #define CONFIG_FSL_ESDHC
45 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
46 #define CONFIG_SYS_FSL_ESDHC_NUM	1
47 
48 #define CONFIG_MMC
49 #define CONFIG_GENERIC_MMC
50 #define CONFIG_DOS_PARTITION
51 
52 /* Eth Configs */
53 #define CONFIG_HAS_ETH1
54 #define CONFIG_MII
55 
56 #define CONFIG_FEC_MXC
57 #define IMX_FEC_BASE	FEC_BASE_ADDR
58 #define CONFIG_FEC_MXC_PHYADDR	0x1F
59 
60 /* allow to overwrite serial and ethaddr */
61 #define CONFIG_ENV_OVERWRITE
62 #define CONFIG_CONS_INDEX		1
63 #define CONFIG_BAUDRATE			115200
64 
65 /* Command definition */
66 
67 #define CONFIG_ETHPRIME		"FEC0"
68 
69 #define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
70 #define CONFIG_SYS_TEXT_BASE    0x77800000
71 
72 #define CONFIG_EXTRA_ENV_SETTINGS \
73 	"script=boot.scr\0" \
74 	"uimage=uImage\0" \
75 	"mmcdev=0\0" \
76 	"mmcpart=2\0" \
77 	"mmcroot=/dev/mmcblk0p3 rw\0" \
78 	"mmcrootfstype=ext3 rootwait\0" \
79 	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
80 		"root=${mmcroot} " \
81 		"rootfstype=${mmcrootfstype}\0" \
82 	"loadbootscript=" \
83 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
84 	"bootscript=echo Running bootscript from mmc ...; " \
85 		"source\0" \
86 	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
87 	"mmcboot=echo Booting from mmc ...; " \
88 		"run mmcargs; " \
89 		"bootm\0" \
90 	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
91 		"root=/dev/nfs " \
92 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
93 	"netboot=echo Booting from net ...; " \
94 		"run netargs; " \
95 		"dhcp ${uimage}; bootm\0" \
96 
97 #define CONFIG_BOOTCOMMAND \
98 	"mmc dev ${mmcdev}; if mmc rescan; then " \
99 		"if run loadbootscript; then " \
100 			"run bootscript; " \
101 		"else " \
102 			"if run loaduimage; then " \
103 				"run mmcboot; " \
104 			"else run netboot; " \
105 			"fi; " \
106 		"fi; " \
107 	"else run netboot; fi"
108 #define CONFIG_ARP_TIMEOUT	200UL
109 
110 /* Miscellaneous configurable options */
111 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
112 #define CONFIG_AUTO_COMPLETE
113 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
114 
115 /* Print Buffer Size */
116 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
117 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
119 
120 #define CONFIG_SYS_MEMTEST_START       0x70000000
121 #define CONFIG_SYS_MEMTEST_END         0x70010000
122 
123 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
124 
125 #define CONFIG_CMDLINE_EDITING
126 
127 /* Physical Memory Map */
128 #define CONFIG_NR_DRAM_BANKS	2
129 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
130 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
131 #define PHYS_SDRAM_2		CSD1_BASE_ADDR
132 #define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
133 #define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
134 
135 #define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
136 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
137 #define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
138 
139 #define CONFIG_SYS_INIT_SP_OFFSET \
140 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_ADDR \
142 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
143 
144 /* FLASH and environment organization */
145 #define CONFIG_SYS_NO_FLASH
146 
147 #define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
148 #define CONFIG_ENV_SIZE        (8 * 1024)
149 #define CONFIG_ENV_IS_IN_MMC
150 #define CONFIG_SYS_MMC_ENV_DEV 0
151 
152 #endif				/* __CONFIG_H */
153