1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ 21 #define CONFIG_MX31 /* in a mx31 */ 22 23 #define CONFIG_SYS_GENERIC_BOARD 24 25 #define CONFIG_DISPLAY_CPUINFO 26 #define CONFIG_DISPLAY_BOARDINFO 27 28 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 32 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 33 34 #define CONFIG_SPL 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 37 #define CONFIG_SPL_MAX_SIZE 2048 38 #define CONFIG_SPL_NAND_SUPPORT 39 #define CONFIG_SPL_LIBGENERIC_SUPPORT 40 41 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 42 #define CONFIG_SYS_TEXT_BASE 0x87e00000 43 44 #ifndef CONFIG_SPL_BUILD 45 #define CONFIG_SKIP_LOWLEVEL_INIT 46 #endif 47 48 /* 49 * Size of malloc() pool 50 */ 51 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 52 53 /* 54 * Hardware drivers 55 */ 56 57 #define CONFIG_MXC_UART 58 #define CONFIG_MXC_UART_BASE UART1_BASE 59 #define CONFIG_MXC_GPIO 60 61 #define CONFIG_HARD_SPI 62 #define CONFIG_MXC_SPI 63 #define CONFIG_DEFAULT_SPI_BUS 1 64 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 65 66 /* PMIC Controller */ 67 #define CONFIG_POWER 68 #define CONFIG_POWER_SPI 69 #define CONFIG_POWER_FSL 70 #define CONFIG_FSL_PMIC_BUS 1 71 #define CONFIG_FSL_PMIC_CS 2 72 #define CONFIG_FSL_PMIC_CLK 1000000 73 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 74 #define CONFIG_FSL_PMIC_BITLEN 32 75 #define CONFIG_RTC_MC13XXX 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_CONS_INDEX 1 80 #define CONFIG_BAUDRATE 115200 81 82 /*********************************************************** 83 * Command definition 84 ***********************************************************/ 85 86 #include <config_cmd_default.h> 87 88 #define CONFIG_CMD_MII 89 #define CONFIG_CMD_PING 90 #define CONFIG_CMD_DHCP 91 #define CONFIG_CMD_SPI 92 #define CONFIG_CMD_DATE 93 #define CONFIG_CMD_NAND 94 #define CONFIG_CMD_BOOTZ 95 96 /* 97 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 98 * that CFG_NO_FLASH is undefined). 99 */ 100 #undef CONFIG_CMD_IMLS 101 102 #define CONFIG_BOARD_LATE_INIT 103 104 #define CONFIG_BOOTDELAY 1 105 106 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 108 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 109 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 110 "bootcmd=run bootcmd_net\0" \ 111 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 112 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 113 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 114 "nand erase 0x0 0x40000; " \ 115 "nand write 0x81000000 0x0 0x40000\0" 116 117 #define CONFIG_SMC911X 118 #define CONFIG_SMC911X_BASE 0xB6000000 119 #define CONFIG_SMC911X_32_BIT 120 121 /* 122 * Miscellaneous configurable options 123 */ 124 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 125 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 126 /* Print Buffer Size */ 127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 128 sizeof(CONFIG_SYS_PROMPT)+16) 129 /* max number of command args */ 130 #define CONFIG_SYS_MAXARGS 16 131 /* Boot Argument Buffer Size */ 132 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 133 134 /* memtest works on */ 135 #define CONFIG_SYS_MEMTEST_START 0x80000000 136 #define CONFIG_SYS_MEMTEST_END 0x80010000 137 138 /* default load address */ 139 #define CONFIG_SYS_LOAD_ADDR 0x81000000 140 141 #define CONFIG_CMDLINE_EDITING 142 143 /*----------------------------------------------------------------------- 144 * Physical Memory Map 145 */ 146 #define CONFIG_NR_DRAM_BANKS 1 147 #define PHYS_SDRAM_1 CSD0_BASE 148 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 149 #define CONFIG_BOARD_EARLY_INIT_F 150 151 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 152 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 153 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 154 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 155 GENERATED_GBL_DATA_SIZE) 156 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 157 CONFIG_SYS_INIT_RAM_SIZE) 158 159 /*----------------------------------------------------------------------- 160 * FLASH and environment organization 161 */ 162 /* No NOR flash present */ 163 #define CONFIG_SYS_NO_FLASH 164 165 #define CONFIG_ENV_IS_IN_NAND 166 #define CONFIG_ENV_OFFSET 0x40000 167 #define CONFIG_ENV_OFFSET_REDUND 0x60000 168 #define CONFIG_ENV_SIZE (128 * 1024) 169 170 /* 171 * NAND driver 172 */ 173 #define CONFIG_NAND_MXC 174 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 175 #define CONFIG_SYS_MAX_NAND_DEVICE 1 176 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 177 #define CONFIG_MXC_NAND_HWECC 178 #define CONFIG_SYS_NAND_LARGEPAGE 179 180 /* NAND configuration for the NAND_SPL */ 181 182 /* Start copying real U-boot from the second page */ 183 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 184 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 185 /* Load U-Boot to this address */ 186 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 187 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 188 189 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 190 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 191 #define CONFIG_SYS_NAND_PAGE_COUNT 64 192 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 193 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 194 195 196 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 197 #define CCM_CCMR_SETUP 0x074B0BF5 198 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 199 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 200 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 201 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 202 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 203 PLL_MFN(12)) 204 205 #define ESDMISC_MDDR_SETUP 0x00000004 206 #define ESDMISC_MDDR_RESET_DL 0x0000000c 207 #define ESDCFG0_MDDR_SETUP 0x006ac73a 208 209 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 210 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 211 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 212 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 213 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 214 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 215 #define ESDCTL_RW ESDCTL_SETTINGS 216 217 #endif /* __CONFIG_H */ 218