1 /* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #include <asm/arch/imx-regs.h> 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MX31 /* This is a mx31 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 25 #define CONFIG_SETUP_MEMORY_TAGS 26 #define CONFIG_INITRD_TAG 27 28 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS 29 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 32 #define CONFIG_SPL_MAX_SIZE 2048 33 34 #define CONFIG_SPL_TEXT_BASE 0x87dc0000 35 #define CONFIG_SYS_TEXT_BASE 0x87e00000 36 37 #ifndef CONFIG_SPL_BUILD 38 #define CONFIG_SKIP_LOWLEVEL_INIT 39 #endif 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 #define CONFIG_MXC_UART 51 #define CONFIG_MXC_UART_BASE UART1_BASE 52 #define CONFIG_MXC_GPIO 53 54 #define CONFIG_HARD_SPI 55 #define CONFIG_MXC_SPI 56 #define CONFIG_DEFAULT_SPI_BUS 1 57 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 58 59 /* PMIC Controller */ 60 #define CONFIG_POWER 61 #define CONFIG_POWER_SPI 62 #define CONFIG_POWER_FSL 63 #define CONFIG_FSL_PMIC_BUS 1 64 #define CONFIG_FSL_PMIC_CS 2 65 #define CONFIG_FSL_PMIC_CLK 1000000 66 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 67 #define CONFIG_FSL_PMIC_BITLEN 32 68 #define CONFIG_RTC_MC13XXX 69 70 /* allow to overwrite serial and ethaddr */ 71 #define CONFIG_ENV_OVERWRITE 72 #define CONFIG_CONS_INDEX 1 73 #define CONFIG_BAUDRATE 115200 74 75 /*********************************************************** 76 * Command definition 77 ***********************************************************/ 78 #define CONFIG_CMD_DATE 79 #define CONFIG_CMD_NAND 80 81 #define CONFIG_BOARD_LATE_INIT 82 83 84 #define CONFIG_EXTRA_ENV_SETTINGS \ 85 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 86 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 87 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 88 "bootcmd=run bootcmd_net\0" \ 89 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 90 "tftpboot 0x81000000 uImage-mx31; bootm\0" \ 91 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ 92 "nand erase 0x0 0x40000; " \ 93 "nand write 0x81000000 0x0 0x40000\0" 94 95 #define CONFIG_SMC911X 96 #define CONFIG_SMC911X_BASE 0xB6000000 97 #define CONFIG_SMC911X_32_BIT 98 99 /* 100 * Miscellaneous configurable options 101 */ 102 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 103 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 104 /* max number of command args */ 105 #define CONFIG_SYS_MAXARGS 16 106 /* Boot Argument Buffer Size */ 107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 108 109 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_START 0x80000000 111 #define CONFIG_SYS_MEMTEST_END 0x80010000 112 113 /* default load address */ 114 #define CONFIG_SYS_LOAD_ADDR 0x81000000 115 116 #define CONFIG_CMDLINE_EDITING 117 118 /*----------------------------------------------------------------------- 119 * Physical Memory Map 120 */ 121 #define CONFIG_NR_DRAM_BANKS 1 122 #define PHYS_SDRAM_1 CSD0_BASE 123 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 124 #define CONFIG_BOARD_EARLY_INIT_F 125 126 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 127 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 128 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 129 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 130 GENERATED_GBL_DATA_SIZE) 131 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 132 CONFIG_SYS_INIT_RAM_SIZE) 133 134 /*----------------------------------------------------------------------- 135 * FLASH and environment organization 136 */ 137 /* No NOR flash present */ 138 #define CONFIG_SYS_NO_FLASH 139 140 #define CONFIG_ENV_IS_IN_NAND 141 #define CONFIG_ENV_OFFSET 0x40000 142 #define CONFIG_ENV_OFFSET_REDUND 0x60000 143 #define CONFIG_ENV_SIZE (128 * 1024) 144 145 /* 146 * NAND driver 147 */ 148 #define CONFIG_NAND_MXC 149 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR 150 #define CONFIG_SYS_MAX_NAND_DEVICE 1 151 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR 152 #define CONFIG_MXC_NAND_HWECC 153 #define CONFIG_SYS_NAND_LARGEPAGE 154 155 /* NAND configuration for the NAND_SPL */ 156 157 /* Start copying real U-Boot from the second page */ 158 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 159 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 160 /* Load U-Boot to this address */ 161 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 162 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 163 164 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 165 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 166 #define CONFIG_SYS_NAND_PAGE_COUNT 64 167 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 168 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 169 170 /* Configuration of lowlevel_init.S (clocks and SDRAM) */ 171 #define CCM_CCMR_SETUP 0x074B0BF5 172 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ 173 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ 174 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ 175 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) 176 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 177 PLL_MFN(12)) 178 179 #define ESDMISC_MDDR_SETUP 0x00000004 180 #define ESDMISC_MDDR_RESET_DL 0x0000000c 181 #define ESDCFG0_MDDR_SETUP 0x006ac73a 182 183 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 184 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 185 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 186 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 187 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 188 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 189 #define ESDCTL_RW ESDCTL_SETTINGS 190 191 #endif /* __CONFIG_H */ 192