xref: /rk3399_rockchip-uboot/include/configs/mx31pdk.h (revision 8449f287f5c53d59db13c3c512e6bd1750b692d1)
1*8449f287SMagnus Lilja /*
2*8449f287SMagnus Lilja  * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3*8449f287SMagnus Lilja  *
4*8449f287SMagnus Lilja  * (C) Copyright 2004
5*8449f287SMagnus Lilja  * Texas Instruments.
6*8449f287SMagnus Lilja  * Richard Woodruff <r-woodruff2@ti.com>
7*8449f287SMagnus Lilja  * Kshitij Gupta <kshitij@ti.com>
8*8449f287SMagnus Lilja  *
9*8449f287SMagnus Lilja  * Configuration settings for the Freescale i.MX31 PDK board.
10*8449f287SMagnus Lilja  *
11*8449f287SMagnus Lilja  * See file CREDITS for list of people who contributed to this
12*8449f287SMagnus Lilja  * project.
13*8449f287SMagnus Lilja  *
14*8449f287SMagnus Lilja  * This program is free software; you can redistribute it and/or
15*8449f287SMagnus Lilja  * modify it under the terms of the GNU General Public License as
16*8449f287SMagnus Lilja  * published by the Free Software Foundation; either version 2 of
17*8449f287SMagnus Lilja  * the License, or (at your option) any later version.
18*8449f287SMagnus Lilja  *
19*8449f287SMagnus Lilja  * This program is distributed in the hope that it will be useful,
20*8449f287SMagnus Lilja  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21*8449f287SMagnus Lilja  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
22*8449f287SMagnus Lilja  * GNU General Public License for more details.
23*8449f287SMagnus Lilja  *
24*8449f287SMagnus Lilja  * You should have received a copy of the GNU General Public License
25*8449f287SMagnus Lilja  * along with this program; if not, write to the Free Software
26*8449f287SMagnus Lilja  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27*8449f287SMagnus Lilja  * MA 02111-1307 USA
28*8449f287SMagnus Lilja  */
29*8449f287SMagnus Lilja 
30*8449f287SMagnus Lilja #ifndef __CONFIG_H
31*8449f287SMagnus Lilja #define __CONFIG_H
32*8449f287SMagnus Lilja 
33*8449f287SMagnus Lilja /* High Level Configuration Options */
34*8449f287SMagnus Lilja #define CONFIG_ARM1136		1	/* This is an arm1136 CPU core */
35*8449f287SMagnus Lilja #define CONFIG_MX31		1	/* in a mx31 */
36*8449f287SMagnus Lilja #define CONFIG_MX31_HCLK_FREQ	26000000
37*8449f287SMagnus Lilja #define CONFIG_MX31_CLK32	32768
38*8449f287SMagnus Lilja 
39*8449f287SMagnus Lilja #define CONFIG_DISPLAY_CPUINFO
40*8449f287SMagnus Lilja #define CONFIG_DISPLAY_BOARDINFO
41*8449f287SMagnus Lilja 
42*8449f287SMagnus Lilja #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
43*8449f287SMagnus Lilja #define CONFIG_SETUP_MEMORY_TAGS	1
44*8449f287SMagnus Lilja #define CONFIG_INITRD_TAG		1
45*8449f287SMagnus Lilja 
46*8449f287SMagnus Lilja /* No support for NAND boot for i.MX31 PDK yet, so we rely on some other
47*8449f287SMagnus Lilja  * program to initialize the SDRAM.
48*8449f287SMagnus Lilja  */
49*8449f287SMagnus Lilja #define CONFIG_SKIP_LOWLEVEL_INIT
50*8449f287SMagnus Lilja 
51*8449f287SMagnus Lilja /*
52*8449f287SMagnus Lilja  * Size of malloc() pool
53*8449f287SMagnus Lilja  */
54*8449f287SMagnus Lilja #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
55*8449f287SMagnus Lilja /* Bytes reserved for initial data */
56*8449f287SMagnus Lilja #define CONFIG_SYS_GBL_DATA_SIZE	128
57*8449f287SMagnus Lilja 
58*8449f287SMagnus Lilja /*
59*8449f287SMagnus Lilja  * Hardware drivers
60*8449f287SMagnus Lilja  */
61*8449f287SMagnus Lilja 
62*8449f287SMagnus Lilja #define CONFIG_MXC_UART		1
63*8449f287SMagnus Lilja #define CONFIG_SYS_MX31_UART1	1
64*8449f287SMagnus Lilja 
65*8449f287SMagnus Lilja #define CONFIG_HARD_SPI		1
66*8449f287SMagnus Lilja #define CONFIG_MXC_SPI		1
67*8449f287SMagnus Lilja #define CONFIG_DEFAULT_SPI_BUS	1
68*8449f287SMagnus Lilja #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
69*8449f287SMagnus Lilja 
70*8449f287SMagnus Lilja #define CONFIG_RTC_MC13783	1
71*8449f287SMagnus Lilja 
72*8449f287SMagnus Lilja /* MC13783 connected to CSPI2 and SS2 */
73*8449f287SMagnus Lilja #define CONFIG_MC13783_SPI_BUS	1
74*8449f287SMagnus Lilja #define CONFIG_MC13783_SPI_CS	2
75*8449f287SMagnus Lilja 
76*8449f287SMagnus Lilja /* allow to overwrite serial and ethaddr */
77*8449f287SMagnus Lilja #define CONFIG_ENV_OVERWRITE
78*8449f287SMagnus Lilja #define CONFIG_CONS_INDEX		1
79*8449f287SMagnus Lilja #define CONFIG_BAUDRATE			115200
80*8449f287SMagnus Lilja #define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
81*8449f287SMagnus Lilja 
82*8449f287SMagnus Lilja /***********************************************************
83*8449f287SMagnus Lilja  * Command definition
84*8449f287SMagnus Lilja  ***********************************************************/
85*8449f287SMagnus Lilja 
86*8449f287SMagnus Lilja #include <config_cmd_default.h>
87*8449f287SMagnus Lilja 
88*8449f287SMagnus Lilja #define CONFIG_CMD_MII
89*8449f287SMagnus Lilja #define CONFIG_CMD_PING
90*8449f287SMagnus Lilja #define CONFIG_CMD_SPI
91*8449f287SMagnus Lilja #define CONFIG_CMD_DATE
92*8449f287SMagnus Lilja 
93*8449f287SMagnus Lilja /*
94*8449f287SMagnus Lilja  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
95*8449f287SMagnus Lilja  * that CFG_NO_FLASH is undefined).
96*8449f287SMagnus Lilja  */
97*8449f287SMagnus Lilja #undef CONFIG_CMD_IMLS
98*8449f287SMagnus Lilja 
99*8449f287SMagnus Lilja #define CONFIG_BOOTDELAY	3
100*8449f287SMagnus Lilja 
101*8449f287SMagnus Lilja #define	CONFIG_EXTRA_ENV_SETTINGS					\
102*8449f287SMagnus Lilja 	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
103*8449f287SMagnus Lilja 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
104*8449f287SMagnus Lilja 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
105*8449f287SMagnus Lilja 	"bootcmd=run bootcmd_net\0"					\
106*8449f287SMagnus Lilja 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
107*8449f287SMagnus Lilja 		"tftpboot 0x81000000 uImage-mx31; bootm\0"
108*8449f287SMagnus Lilja 
109*8449f287SMagnus Lilja #define CONFIG_DRIVER_SMC911X		1
110*8449f287SMagnus Lilja #define CONFIG_DRIVER_SMC911X_BASE	0xB6000000
111*8449f287SMagnus Lilja #define CONFIG_DRIVER_SMC911X_32_BIT	1
112*8449f287SMagnus Lilja 
113*8449f287SMagnus Lilja /*
114*8449f287SMagnus Lilja  * Miscellaneous configurable options
115*8449f287SMagnus Lilja  */
116*8449f287SMagnus Lilja #define CONFIG_SYS_LONGHELP	/* undef to save memory */
117*8449f287SMagnus Lilja #define CONFIG_SYS_PROMPT	"uboot> "
118*8449f287SMagnus Lilja #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
119*8449f287SMagnus Lilja /* Print Buffer Size */
120*8449f287SMagnus Lilja #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
121*8449f287SMagnus Lilja 				sizeof(CONFIG_SYS_PROMPT)+16)
122*8449f287SMagnus Lilja /* max number of command args */
123*8449f287SMagnus Lilja #define CONFIG_SYS_MAXARGS	16
124*8449f287SMagnus Lilja /* Boot Argument Buffer Size */
125*8449f287SMagnus Lilja #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
126*8449f287SMagnus Lilja 
127*8449f287SMagnus Lilja /* memtest works on */
128*8449f287SMagnus Lilja #define CONFIG_SYS_MEMTEST_START	0x80000000
129*8449f287SMagnus Lilja #define CONFIG_SYS_MEMTEST_END		0x10000
130*8449f287SMagnus Lilja 
131*8449f287SMagnus Lilja /* default load address */
132*8449f287SMagnus Lilja #define CONFIG_SYS_LOAD_ADDR		0x81000000
133*8449f287SMagnus Lilja 
134*8449f287SMagnus Lilja #define CONFIG_SYS_HZ			1000
135*8449f287SMagnus Lilja 
136*8449f287SMagnus Lilja #define CONFIG_CMDLINE_EDITING	1
137*8449f287SMagnus Lilja 
138*8449f287SMagnus Lilja /*-----------------------------------------------------------------------
139*8449f287SMagnus Lilja  * Stack sizes
140*8449f287SMagnus Lilja  *
141*8449f287SMagnus Lilja  * The stack sizes are set up in start.S using the settings below
142*8449f287SMagnus Lilja  */
143*8449f287SMagnus Lilja #define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */
144*8449f287SMagnus Lilja 
145*8449f287SMagnus Lilja /*-----------------------------------------------------------------------
146*8449f287SMagnus Lilja  * Physical Memory Map
147*8449f287SMagnus Lilja  */
148*8449f287SMagnus Lilja #define CONFIG_NR_DRAM_BANKS	1
149*8449f287SMagnus Lilja #define PHYS_SDRAM_1		CSD0_BASE
150*8449f287SMagnus Lilja #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
151*8449f287SMagnus Lilja 
152*8449f287SMagnus Lilja /*-----------------------------------------------------------------------
153*8449f287SMagnus Lilja  * FLASH and environment organization
154*8449f287SMagnus Lilja  */
155*8449f287SMagnus Lilja /* No NOR flash present */
156*8449f287SMagnus Lilja #define CONFIG_SYS_NO_FLASH	1
157*8449f287SMagnus Lilja 
158*8449f287SMagnus Lilja #define CONFIG_ENV_IS_NOWHERE	1
159*8449f287SMagnus Lilja 
160*8449f287SMagnus Lilja #define CONFIG_ENV_SIZE		(128 * 1024)
161*8449f287SMagnus Lilja 
162*8449f287SMagnus Lilja #endif /* __CONFIG_H */
163