1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * Configuration settings for the MX31ADS Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch/imx-regs.h> 13 14 /* High Level Configuration Options */ 15 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 16 #define CONFIG_MX31 1 /* in a mx31 */ 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SYS_TEXT_BASE 0xA0000000 22 23 #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS 24 25 /* 26 * Disabled for now due to build problems under Debian and a significant increase 27 * in the final file size: 144260 vs. 109536 Bytes. 28 */ 29 #if 0 30 #define CONFIG_OF_LIBFDT 1 31 #define CONFIG_FIT 1 32 #define CONFIG_FIT_VERBOSE 1 33 #endif 34 35 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 1 37 #define CONFIG_INITRD_TAG 1 38 39 /* 40 * Size of malloc() pool 41 */ 42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 43 44 /* 45 * Hardware drivers 46 */ 47 48 #define CONFIG_MXC_UART 49 #define CONFIG_MXC_UART_BASE UART1_BASE 50 51 #define CONFIG_HARD_SPI 1 52 #define CONFIG_MXC_SPI 1 53 #define CONFIG_DEFAULT_SPI_BUS 1 54 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 55 #define CONFIG_MXC_GPIO 56 57 /* PMIC Controller */ 58 #define CONFIG_POWER 59 #define CONFIG_POWER_SPI 60 #define CONFIG_POWER_FSL 61 #define CONFIG_FSL_PMIC_BUS 1 62 #define CONFIG_FSL_PMIC_CS 0 63 #define CONFIG_FSL_PMIC_CLK 1000000 64 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 65 #define CONFIG_FSL_PMIC_BITLEN 32 66 #define CONFIG_RTC_MC13XXX 67 68 /* allow to overwrite serial and ethaddr */ 69 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_CONS_INDEX 1 71 #define CONFIG_BAUDRATE 115200 72 73 /*********************************************************** 74 * Command definition 75 ***********************************************************/ 76 77 #include <config_cmd_default.h> 78 79 #define CONFIG_CMD_PING 80 #define CONFIG_CMD_DHCP 81 #define CONFIG_CMD_SPI 82 #define CONFIG_CMD_DATE 83 84 #define CONFIG_BOOTDELAY 3 85 86 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 87 88 #define CONFIG_EXTRA_ENV_SETTINGS \ 89 "netdev=eth0\0" \ 90 "uboot_addr=0xa0000000\0" \ 91 "uboot=mx31ads/u-boot.bin\0" \ 92 "kernel=mx31ads/uImage\0" \ 93 "nfsroot=/opt/eldk/arm\0" \ 94 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 95 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 96 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 97 "bootcmd=run bootcmd_net\0" \ 98 "bootcmd_net=run bootargs_base bootargs_nfs; " \ 99 "tftpboot ${loadaddr} ${kernel}; bootm\0" \ 100 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ 101 "protect off ${uboot_addr} 0xa003ffff; " \ 102 "erase ${uboot_addr} 0xa003ffff; " \ 103 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ 104 "setenv filesize; saveenv\0" 105 106 #define CONFIG_CS8900 107 #define CONFIG_CS8900_BASE 0xb4020300 108 #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ 109 110 /* 111 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under 112 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A 113 * controller inverted. The controller is capable of detecting and correcting 114 * this, but it needs 4 network packets for that. Which means, at startup, you 115 * will not receive answers to the first 4 packest, unless there have been some 116 * broadcasts on the network, or your board is on a hub. Reducing the ARP 117 * timeout from default 5 seconds to 200ms we speed up the initial TFTP 118 * transfer, should the user wish one, significantly. 119 */ 120 #define CONFIG_ARP_TIMEOUT 200UL 121 122 /* 123 * Miscellaneous configurable options 124 */ 125 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 126 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 127 /* Print Buffer Size */ 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 129 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 131 132 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 133 #define CONFIG_SYS_MEMTEST_END 0x10000 134 135 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 136 137 #define CONFIG_CMDLINE_EDITING 1 138 139 /*----------------------------------------------------------------------- 140 * Physical Memory Map 141 */ 142 #define CONFIG_NR_DRAM_BANKS 1 143 #define PHYS_SDRAM_1 CSD0_BASE 144 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 145 #define CONFIG_BOARD_EARLY_INIT_F 146 147 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 148 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 149 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 150 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 151 GENERATED_GBL_DATA_SIZE) 152 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 153 CONFIG_SYS_GBL_DATA_OFFSET) 154 155 /*----------------------------------------------------------------------- 156 * FLASH and environment organization 157 */ 158 #define CONFIG_SYS_FLASH_BASE CS0_BASE 159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 160 #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 162 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ 163 164 #define CONFIG_ENV_IS_IN_FLASH 1 165 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 166 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 167 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 168 169 /* Address and size of Redundant Environment Sector */ 170 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 171 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 172 173 174 /*----------------------------------------------------------------------- 175 * CFI FLASH driver setup 176 */ 177 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 178 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 179 #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 181 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 182 183 /* 184 * JFFS2 partitions 185 */ 186 #undef CONFIG_CMD_MTDPARTS 187 #define CONFIG_JFFS2_DEV "nor0" 188 189 #endif /* __CONFIG_H */ 190