1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * Configuration settings for the MX31ADS Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch/imx-regs.h> 13 14 /* High Level Configuration Options */ 15 #define CONFIG_MX31 1 /* This is a mx31 */ 16 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SYS_TEXT_BASE 0xA0000000 22 23 #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS 24 25 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 1 27 #define CONFIG_INITRD_TAG 1 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 33 34 /* 35 * Hardware drivers 36 */ 37 38 #define CONFIG_MXC_UART 39 #define CONFIG_MXC_UART_BASE UART1_BASE 40 41 #define CONFIG_HARD_SPI 1 42 #define CONFIG_MXC_SPI 1 43 #define CONFIG_DEFAULT_SPI_BUS 1 44 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 45 #define CONFIG_MXC_GPIO 46 47 /* PMIC Controller */ 48 #define CONFIG_POWER 49 #define CONFIG_POWER_SPI 50 #define CONFIG_POWER_FSL 51 #define CONFIG_FSL_PMIC_BUS 1 52 #define CONFIG_FSL_PMIC_CS 0 53 #define CONFIG_FSL_PMIC_CLK 1000000 54 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 55 #define CONFIG_FSL_PMIC_BITLEN 32 56 #define CONFIG_RTC_MC13XXX 57 58 /* allow to overwrite serial and ethaddr */ 59 #define CONFIG_ENV_OVERWRITE 60 #define CONFIG_CONS_INDEX 1 61 #define CONFIG_BAUDRATE 115200 62 63 /*********************************************************** 64 * Command definition 65 ***********************************************************/ 66 #define CONFIG_CMD_PING 67 #define CONFIG_CMD_DHCP 68 #define CONFIG_CMD_SPI 69 #define CONFIG_CMD_DATE 70 71 #define CONFIG_BOOTDELAY 3 72 73 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 74 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 "netdev=eth0\0" \ 77 "uboot_addr=0xa0000000\0" \ 78 "uboot=mx31ads/u-boot.bin\0" \ 79 "kernel=mx31ads/uImage\0" \ 80 "nfsroot=/opt/eldk/arm\0" \ 81 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 82 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 83 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 84 "bootcmd=run bootcmd_net\0" \ 85 "bootcmd_net=run bootargs_base bootargs_nfs; " \ 86 "tftpboot ${loadaddr} ${kernel}; bootm\0" \ 87 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ 88 "protect off ${uboot_addr} 0xa003ffff; " \ 89 "erase ${uboot_addr} 0xa003ffff; " \ 90 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ 91 "setenv filesize; saveenv\0" 92 93 #define CONFIG_CS8900 94 #define CONFIG_CS8900_BASE 0xb4020300 95 #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ 96 97 /* 98 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under 99 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A 100 * controller inverted. The controller is capable of detecting and correcting 101 * this, but it needs 4 network packets for that. Which means, at startup, you 102 * will not receive answers to the first 4 packest, unless there have been some 103 * broadcasts on the network, or your board is on a hub. Reducing the ARP 104 * timeout from default 5 seconds to 200ms we speed up the initial TFTP 105 * transfer, should the user wish one, significantly. 106 */ 107 #define CONFIG_ARP_TIMEOUT 200UL 108 109 /* 110 * Miscellaneous configurable options 111 */ 112 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 113 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 114 /* Print Buffer Size */ 115 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 116 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 118 119 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 120 #define CONFIG_SYS_MEMTEST_END 0x10000 121 122 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 123 124 #define CONFIG_CMDLINE_EDITING 1 125 126 /*----------------------------------------------------------------------- 127 * Physical Memory Map 128 */ 129 #define CONFIG_NR_DRAM_BANKS 1 130 #define PHYS_SDRAM_1 CSD0_BASE 131 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 132 #define CONFIG_BOARD_EARLY_INIT_F 133 134 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 135 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 136 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 137 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 138 GENERATED_GBL_DATA_SIZE) 139 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 140 CONFIG_SYS_GBL_DATA_OFFSET) 141 142 /*----------------------------------------------------------------------- 143 * FLASH and environment organization 144 */ 145 #define CONFIG_SYS_FLASH_BASE CS0_BASE 146 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 147 #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ 148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 149 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ 150 151 #define CONFIG_ENV_IS_IN_FLASH 1 152 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 153 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 154 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 155 156 /* Address and size of Redundant Environment Sector */ 157 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 158 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 159 160 161 /*----------------------------------------------------------------------- 162 * CFI FLASH driver setup 163 */ 164 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 165 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 166 #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ 167 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 168 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 169 170 /* 171 * JFFS2 partitions 172 */ 173 #undef CONFIG_CMD_MTDPARTS 174 #define CONFIG_JFFS2_DEV "nor0" 175 176 #endif /* __CONFIG_H */ 177