1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * Configuration settings for the MX31ADS Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch/imx-regs.h> 13 14 /* High Level Configuration Options */ 15 #define CONFIG_MX31 1 /* This is a mx31 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0xA0000000 18 19 #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS 20 21 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 22 #define CONFIG_SETUP_MEMORY_TAGS 1 23 #define CONFIG_INITRD_TAG 1 24 25 /* 26 * Size of malloc() pool 27 */ 28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 29 30 /* 31 * Hardware drivers 32 */ 33 34 #define CONFIG_MXC_UART 35 #define CONFIG_MXC_UART_BASE UART1_BASE 36 37 #define CONFIG_HARD_SPI 1 38 #define CONFIG_MXC_SPI 1 39 #define CONFIG_DEFAULT_SPI_BUS 1 40 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 41 #define CONFIG_MXC_GPIO 42 43 /* PMIC Controller */ 44 #define CONFIG_POWER 45 #define CONFIG_POWER_SPI 46 #define CONFIG_POWER_FSL 47 #define CONFIG_FSL_PMIC_BUS 1 48 #define CONFIG_FSL_PMIC_CS 0 49 #define CONFIG_FSL_PMIC_CLK 1000000 50 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 51 #define CONFIG_FSL_PMIC_BITLEN 32 52 #define CONFIG_RTC_MC13XXX 53 54 /* allow to overwrite serial and ethaddr */ 55 #define CONFIG_ENV_OVERWRITE 56 #define CONFIG_CONS_INDEX 1 57 #define CONFIG_BAUDRATE 115200 58 59 /*********************************************************** 60 * Command definition 61 ***********************************************************/ 62 #define CONFIG_CMD_DATE 63 64 65 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 66 67 #define CONFIG_EXTRA_ENV_SETTINGS \ 68 "netdev=eth0\0" \ 69 "uboot_addr=0xa0000000\0" \ 70 "uboot=mx31ads/u-boot.bin\0" \ 71 "kernel=mx31ads/uImage\0" \ 72 "nfsroot=/opt/eldk/arm\0" \ 73 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 74 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 75 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 76 "bootcmd=run bootcmd_net\0" \ 77 "bootcmd_net=run bootargs_base bootargs_nfs; " \ 78 "tftpboot ${loadaddr} ${kernel}; bootm\0" \ 79 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ 80 "protect off ${uboot_addr} 0xa003ffff; " \ 81 "erase ${uboot_addr} 0xa003ffff; " \ 82 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ 83 "setenv filesize; saveenv\0" 84 85 #define CONFIG_CS8900 86 #define CONFIG_CS8900_BASE 0xb4020300 87 #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ 88 89 /* 90 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under 91 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A 92 * controller inverted. The controller is capable of detecting and correcting 93 * this, but it needs 4 network packets for that. Which means, at startup, you 94 * will not receive answers to the first 4 packest, unless there have been some 95 * broadcasts on the network, or your board is on a hub. Reducing the ARP 96 * timeout from default 5 seconds to 200ms we speed up the initial TFTP 97 * transfer, should the user wish one, significantly. 98 */ 99 #define CONFIG_ARP_TIMEOUT 200UL 100 101 /* 102 * Miscellaneous configurable options 103 */ 104 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 106 /* Print Buffer Size */ 107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 108 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 110 111 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 112 #define CONFIG_SYS_MEMTEST_END 0x10000 113 114 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 115 116 #define CONFIG_CMDLINE_EDITING 1 117 118 /*----------------------------------------------------------------------- 119 * Physical Memory Map 120 */ 121 #define CONFIG_NR_DRAM_BANKS 1 122 #define PHYS_SDRAM_1 CSD0_BASE 123 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 124 125 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 126 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 127 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 129 GENERATED_GBL_DATA_SIZE) 130 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 131 CONFIG_SYS_GBL_DATA_OFFSET) 132 133 /*----------------------------------------------------------------------- 134 * FLASH and environment organization 135 */ 136 #define CONFIG_SYS_FLASH_BASE CS0_BASE 137 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 138 #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 140 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ 141 142 #define CONFIG_ENV_IS_IN_FLASH 1 143 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 144 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 145 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 146 147 /* Address and size of Redundant Environment Sector */ 148 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 149 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 150 151 /*----------------------------------------------------------------------- 152 * CFI FLASH driver setup 153 */ 154 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 155 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 156 #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ 157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 158 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 159 160 /* 161 * JFFS2 partitions 162 */ 163 #undef CONFIG_CMD_MTDPARTS 164 #define CONFIG_JFFS2_DEV "nor0" 165 166 #endif /* __CONFIG_H */ 167