1 /* 2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3 * 4 * Configuration settings for the MX31ADS Freescale board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch/imx-regs.h> 13 14 /* High Level Configuration Options */ 15 #define CONFIG_MX31 1 /* This is a mx31 */ 16 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SYS_TEXT_BASE 0xA0000000 20 21 #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS 22 23 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 24 #define CONFIG_SETUP_MEMORY_TAGS 1 25 #define CONFIG_INITRD_TAG 1 26 27 /* 28 * Size of malloc() pool 29 */ 30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 31 32 /* 33 * Hardware drivers 34 */ 35 36 #define CONFIG_MXC_UART 37 #define CONFIG_MXC_UART_BASE UART1_BASE 38 39 #define CONFIG_HARD_SPI 1 40 #define CONFIG_MXC_SPI 1 41 #define CONFIG_DEFAULT_SPI_BUS 1 42 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 43 #define CONFIG_MXC_GPIO 44 45 /* PMIC Controller */ 46 #define CONFIG_POWER 47 #define CONFIG_POWER_SPI 48 #define CONFIG_POWER_FSL 49 #define CONFIG_FSL_PMIC_BUS 1 50 #define CONFIG_FSL_PMIC_CS 0 51 #define CONFIG_FSL_PMIC_CLK 1000000 52 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 53 #define CONFIG_FSL_PMIC_BITLEN 32 54 #define CONFIG_RTC_MC13XXX 55 56 /* allow to overwrite serial and ethaddr */ 57 #define CONFIG_ENV_OVERWRITE 58 #define CONFIG_CONS_INDEX 1 59 #define CONFIG_BAUDRATE 115200 60 61 /*********************************************************** 62 * Command definition 63 ***********************************************************/ 64 #define CONFIG_CMD_DATE 65 66 67 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 68 69 #define CONFIG_EXTRA_ENV_SETTINGS \ 70 "netdev=eth0\0" \ 71 "uboot_addr=0xa0000000\0" \ 72 "uboot=mx31ads/u-boot.bin\0" \ 73 "kernel=mx31ads/uImage\0" \ 74 "nfsroot=/opt/eldk/arm\0" \ 75 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 76 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 77 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 78 "bootcmd=run bootcmd_net\0" \ 79 "bootcmd_net=run bootargs_base bootargs_nfs; " \ 80 "tftpboot ${loadaddr} ${kernel}; bootm\0" \ 81 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ 82 "protect off ${uboot_addr} 0xa003ffff; " \ 83 "erase ${uboot_addr} 0xa003ffff; " \ 84 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ 85 "setenv filesize; saveenv\0" 86 87 #define CONFIG_CS8900 88 #define CONFIG_CS8900_BASE 0xb4020300 89 #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ 90 91 /* 92 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under 93 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A 94 * controller inverted. The controller is capable of detecting and correcting 95 * this, but it needs 4 network packets for that. Which means, at startup, you 96 * will not receive answers to the first 4 packest, unless there have been some 97 * broadcasts on the network, or your board is on a hub. Reducing the ARP 98 * timeout from default 5 seconds to 200ms we speed up the initial TFTP 99 * transfer, should the user wish one, significantly. 100 */ 101 #define CONFIG_ARP_TIMEOUT 200UL 102 103 /* 104 * Miscellaneous configurable options 105 */ 106 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 107 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 108 /* Print Buffer Size */ 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 112 113 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 114 #define CONFIG_SYS_MEMTEST_END 0x10000 115 116 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 117 118 #define CONFIG_CMDLINE_EDITING 1 119 120 /*----------------------------------------------------------------------- 121 * Physical Memory Map 122 */ 123 #define CONFIG_NR_DRAM_BANKS 1 124 #define PHYS_SDRAM_1 CSD0_BASE 125 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 126 #define CONFIG_BOARD_EARLY_INIT_F 127 128 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 129 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 130 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 132 GENERATED_GBL_DATA_SIZE) 133 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 134 CONFIG_SYS_GBL_DATA_OFFSET) 135 136 /*----------------------------------------------------------------------- 137 * FLASH and environment organization 138 */ 139 #define CONFIG_SYS_FLASH_BASE CS0_BASE 140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 141 #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 143 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ 144 145 #define CONFIG_ENV_IS_IN_FLASH 1 146 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 147 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 148 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 149 150 /* Address and size of Redundant Environment Sector */ 151 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 152 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 153 154 /*----------------------------------------------------------------------- 155 * CFI FLASH driver setup 156 */ 157 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 158 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 159 #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ 160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 161 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 162 163 /* 164 * JFFS2 partitions 165 */ 166 #undef CONFIG_CMD_MTDPARTS 167 #define CONFIG_JFFS2_DEV "nor0" 168 169 #endif /* __CONFIG_H */ 170