1633fa0e7SStefan Roese /* 2633fa0e7SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3633fa0e7SStefan Roese * 4633fa0e7SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5633fa0e7SStefan Roese */ 6633fa0e7SStefan Roese 7633fa0e7SStefan Roese #ifndef _CONFIG_MVEBU_ARMADA_8K_H 8633fa0e7SStefan Roese #define _CONFIG_MVEBU_ARMADA_8K_H 9633fa0e7SStefan Roese 10633fa0e7SStefan Roese /* 11633fa0e7SStefan Roese * High Level Configuration Options (easy to change) 12633fa0e7SStefan Roese */ 13633fa0e7SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 14633fa0e7SStefan Roese 15633fa0e7SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 16633fa0e7SStefan Roese 17633fa0e7SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00000000 18633fa0e7SStefan Roese 19633fa0e7SStefan Roese /* additions for new ARM relocation support */ 20633fa0e7SStefan Roese #define CONFIG_SYS_SDRAM_BASE 0x00000000 21633fa0e7SStefan Roese 22633fa0e7SStefan Roese #define CONFIG_NR_DRAM_BANKS 1 23633fa0e7SStefan Roese 24633fa0e7SStefan Roese /* auto boot */ 25633fa0e7SStefan Roese #define CONFIG_PREBOOT 26633fa0e7SStefan Roese 27633fa0e7SStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 28633fa0e7SStefan Roese 115200, 230400, 460800, 921600 } 29633fa0e7SStefan Roese 30633fa0e7SStefan Roese /* 31633fa0e7SStefan Roese * For booting Linux, the board info and command line data 32633fa0e7SStefan Roese * have to be in the first 8 MB of memory, since this is 33633fa0e7SStefan Roese * the maximum mapped by the Linux kernel during initialization. 34633fa0e7SStefan Roese */ 35633fa0e7SStefan Roese #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36633fa0e7SStefan Roese #define CONFIG_INITRD_TAG /* enable INITRD tag */ 37633fa0e7SStefan Roese #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ 38633fa0e7SStefan Roese 39633fa0e7SStefan Roese #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 40633fa0e7SStefan Roese #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 41633fa0e7SStefan Roese +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 42633fa0e7SStefan Roese 43633fa0e7SStefan Roese /* 44633fa0e7SStefan Roese * Size of malloc() pool 45633fa0e7SStefan Roese */ 46633fa0e7SStefan Roese #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ 47633fa0e7SStefan Roese 48633fa0e7SStefan Roese /* 49633fa0e7SStefan Roese * Other required minimal configurations 50633fa0e7SStefan Roese */ 51633fa0e7SStefan Roese #define CONFIG_SYS_LONGHELP 52633fa0e7SStefan Roese #define CONFIG_AUTO_COMPLETE 53633fa0e7SStefan Roese #define CONFIG_CMDLINE_EDITING 54633fa0e7SStefan Roese #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 55633fa0e7SStefan Roese #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ 56633fa0e7SStefan Roese #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ 57633fa0e7SStefan Roese #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ 58633fa0e7SStefan Roese #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 59633fa0e7SStefan Roese #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 60633fa0e7SStefan Roese 61633fa0e7SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 62633fa0e7SStefan Roese 63633fa0e7SStefan Roese /* End of 16M scrubbed by training in bootrom */ 64633fa0e7SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) 65633fa0e7SStefan Roese 66633fa0e7SStefan Roese /* 67633fa0e7SStefan Roese * SPI Flash configuration 68633fa0e7SStefan Roese */ 69633fa0e7SStefan Roese #define CONFIG_KIRKWOOD_SPI 70633fa0e7SStefan Roese #define CONFIG_ENV_SPI_BUS 0 71633fa0e7SStefan Roese #define CONFIG_ENV_SPI_CS 0 72633fa0e7SStefan Roese 73633fa0e7SStefan Roese /* SPI NOR flash default params, used by sf commands */ 74633fa0e7SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 75633fa0e7SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 76633fa0e7SStefan Roese #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 77633fa0e7SStefan Roese 78633fa0e7SStefan Roese /* Environment in SPI NOR flash */ 79*f59472e8SKonstantin Porotchkin #ifdef CONFIG_MVEBU_SPI_BOOT 80633fa0e7SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 81*f59472e8SKonstantin Porotchkin /* Environment in NAND flash */ 82*f59472e8SKonstantin Porotchkin #elif defined(CONFIG_MVEBU_NAND_BOOT) 83*f59472e8SKonstantin Porotchkin #define CONFIG_ENV_IS_IN_NAND 84*f59472e8SKonstantin Porotchkin #endif 85*f59472e8SKonstantin Porotchkin 86633fa0e7SStefan Roese #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ 87633fa0e7SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 88633fa0e7SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 89633fa0e7SStefan Roese 90*f59472e8SKonstantin Porotchkin #define CONFIG_SYS_MAX_NAND_DEVICE 1 91*f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_MAX_CHIPS 1 92*f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_ONFI_DETECTION 93*f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_USE_FLASH_BBT 94*f59472e8SKonstantin Porotchkin 95def84429SStefan Roese /* 96def84429SStefan Roese * Ethernet Driver configuration 97def84429SStefan Roese */ 98def84429SStefan Roese #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 99def84429SStefan Roese #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ 100def84429SStefan Roese #define CONFIG_ARP_TIMEOUT 200 101def84429SStefan Roese #define CONFIG_NET_RETRY_COUNT 50 102def84429SStefan Roese 103633fa0e7SStefan Roese /* USB 2.0 */ 104633fa0e7SStefan Roese #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 105633fa0e7SStefan Roese 106633fa0e7SStefan Roese /* USB 3.0 */ 107633fa0e7SStefan Roese #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3 108633fa0e7SStefan Roese 109633fa0e7SStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT (CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS + \ 110633fa0e7SStefan Roese CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) 111633fa0e7SStefan Roese 112633fa0e7SStefan Roese /* USB ethernet */ 113633fa0e7SStefan Roese #define CONFIG_USB_HOST_ETHER 114633fa0e7SStefan Roese #define CONFIG_USB_ETHER_ASIX 115633fa0e7SStefan Roese #define CONFIG_USB_ETHER_MCS7830 116633fa0e7SStefan Roese #define CONFIG_USB_ETHER_RTL8152 117633fa0e7SStefan Roese #define CONFIG_USB_ETHER_SMSC95XX 118633fa0e7SStefan Roese 119633fa0e7SStefan Roese /* 120633fa0e7SStefan Roese * SATA/SCSI/AHCI configuration 121633fa0e7SStefan Roese */ 122633fa0e7SStefan Roese #define CONFIG_SCSI 123633fa0e7SStefan Roese #define CONFIG_SCSI_AHCI 124633fa0e7SStefan Roese #define CONFIG_SCSI_AHCI_PLAT 125633fa0e7SStefan Roese #define CONFIG_LIBATA 126633fa0e7SStefan Roese #define CONFIG_LBA48 127633fa0e7SStefan Roese #define CONFIG_SYS_64BIT_LBA 128633fa0e7SStefan Roese 129633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 130633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_LUN 1 131633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 132633fa0e7SStefan Roese CONFIG_SYS_SCSI_MAX_LUN) 133633fa0e7SStefan Roese 134633fa0e7SStefan Roese #define CONFIG_SUPPORT_VFAT 135633fa0e7SStefan Roese 1361ec5aa63SStefan Roese /* 1371ec5aa63SStefan Roese * PCI configuration 1381ec5aa63SStefan Roese */ 1391ec5aa63SStefan Roese #ifdef CONFIG_PCIE_DW_MVEBU 1401ec5aa63SStefan Roese #define CONFIG_E1000 1411ec5aa63SStefan Roese #define CONFIG_CMD_PCI 1421ec5aa63SStefan Roese #endif 1431ec5aa63SStefan Roese 144633fa0e7SStefan Roese #endif /* _CONFIG_MVEBU_ARMADA_8K_H */ 145