1633fa0e7SStefan Roese /* 2633fa0e7SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3633fa0e7SStefan Roese * 4633fa0e7SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5633fa0e7SStefan Roese */ 6633fa0e7SStefan Roese 7633fa0e7SStefan Roese #ifndef _CONFIG_MVEBU_ARMADA_8K_H 8633fa0e7SStefan Roese #define _CONFIG_MVEBU_ARMADA_8K_H 9633fa0e7SStefan Roese 10633fa0e7SStefan Roese /* 11633fa0e7SStefan Roese * High Level Configuration Options (easy to change) 12633fa0e7SStefan Roese */ 13633fa0e7SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 14633fa0e7SStefan Roese 15633fa0e7SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 16633fa0e7SStefan Roese 17633fa0e7SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00000000 18633fa0e7SStefan Roese 19633fa0e7SStefan Roese /* additions for new ARM relocation support */ 20633fa0e7SStefan Roese #define CONFIG_SYS_SDRAM_BASE 0x00000000 21633fa0e7SStefan Roese 22633fa0e7SStefan Roese #define CONFIG_NR_DRAM_BANKS 1 23633fa0e7SStefan Roese 24633fa0e7SStefan Roese /* auto boot */ 25633fa0e7SStefan Roese #define CONFIG_PREBOOT 26633fa0e7SStefan Roese 27633fa0e7SStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 28633fa0e7SStefan Roese 115200, 230400, 460800, 921600 } 29633fa0e7SStefan Roese 30633fa0e7SStefan Roese /* 31633fa0e7SStefan Roese * For booting Linux, the board info and command line data 32633fa0e7SStefan Roese * have to be in the first 8 MB of memory, since this is 33633fa0e7SStefan Roese * the maximum mapped by the Linux kernel during initialization. 34633fa0e7SStefan Roese */ 35633fa0e7SStefan Roese #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36633fa0e7SStefan Roese #define CONFIG_INITRD_TAG /* enable INITRD tag */ 37633fa0e7SStefan Roese #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ 38633fa0e7SStefan Roese 39633fa0e7SStefan Roese #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 40633fa0e7SStefan Roese 41633fa0e7SStefan Roese /* 42633fa0e7SStefan Roese * Size of malloc() pool 43633fa0e7SStefan Roese */ 44633fa0e7SStefan Roese #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ 45633fa0e7SStefan Roese 46633fa0e7SStefan Roese /* 47633fa0e7SStefan Roese * Other required minimal configurations 48633fa0e7SStefan Roese */ 49633fa0e7SStefan Roese #define CONFIG_SYS_LONGHELP 50633fa0e7SStefan Roese #define CONFIG_AUTO_COMPLETE 51633fa0e7SStefan Roese #define CONFIG_CMDLINE_EDITING 52633fa0e7SStefan Roese #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 53633fa0e7SStefan Roese #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ 54633fa0e7SStefan Roese #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ 55633fa0e7SStefan Roese #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ 56633fa0e7SStefan Roese #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 57633fa0e7SStefan Roese #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 58633fa0e7SStefan Roese 59633fa0e7SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 60633fa0e7SStefan Roese 61633fa0e7SStefan Roese /* End of 16M scrubbed by training in bootrom */ 62633fa0e7SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) 63633fa0e7SStefan Roese 64633fa0e7SStefan Roese /* 65633fa0e7SStefan Roese * SPI Flash configuration 66633fa0e7SStefan Roese */ 67633fa0e7SStefan Roese #define CONFIG_ENV_SPI_BUS 0 68633fa0e7SStefan Roese #define CONFIG_ENV_SPI_CS 0 69633fa0e7SStefan Roese 70633fa0e7SStefan Roese /* SPI NOR flash default params, used by sf commands */ 71633fa0e7SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 72633fa0e7SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 73633fa0e7SStefan Roese #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 74633fa0e7SStefan Roese 75633fa0e7SStefan Roese /* Environment in SPI NOR flash */ 76f59472e8SKonstantin Porotchkin #ifdef CONFIG_MVEBU_SPI_BOOT 77f59472e8SKonstantin Porotchkin /* Environment in NAND flash */ 78f59472e8SKonstantin Porotchkin #endif 79f59472e8SKonstantin Porotchkin 80633fa0e7SStefan Roese #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ 81633fa0e7SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 82633fa0e7SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 83633fa0e7SStefan Roese 84f59472e8SKonstantin Porotchkin #define CONFIG_SYS_MAX_NAND_DEVICE 1 85f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_MAX_CHIPS 1 86f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_ONFI_DETECTION 87f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_USE_FLASH_BBT 88f59472e8SKonstantin Porotchkin 89def84429SStefan Roese /* 90def84429SStefan Roese * Ethernet Driver configuration 91def84429SStefan Roese */ 92def84429SStefan Roese #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 93def84429SStefan Roese #define CONFIG_ARP_TIMEOUT 200 94def84429SStefan Roese #define CONFIG_NET_RETRY_COUNT 50 95def84429SStefan Roese 96*cbb89ed0SBin Meng #define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) 97633fa0e7SStefan Roese 98633fa0e7SStefan Roese /* USB ethernet */ 99633fa0e7SStefan Roese 100633fa0e7SStefan Roese /* 101633fa0e7SStefan Roese * SATA/SCSI/AHCI configuration 102633fa0e7SStefan Roese */ 103633fa0e7SStefan Roese #define CONFIG_SCSI_AHCI 104633fa0e7SStefan Roese #define CONFIG_SCSI_AHCI_PLAT 105633fa0e7SStefan Roese #define CONFIG_LIBATA 106633fa0e7SStefan Roese #define CONFIG_LBA48 107633fa0e7SStefan Roese #define CONFIG_SYS_64BIT_LBA 108633fa0e7SStefan Roese 109633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 110633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_LUN 1 111633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 112633fa0e7SStefan Roese CONFIG_SYS_SCSI_MAX_LUN) 113633fa0e7SStefan Roese 114633fa0e7SStefan Roese #define CONFIG_SUPPORT_VFAT 115633fa0e7SStefan Roese 1161ec5aa63SStefan Roese /* 1171ec5aa63SStefan Roese * PCI configuration 1181ec5aa63SStefan Roese */ 1191ec5aa63SStefan Roese #ifdef CONFIG_PCIE_DW_MVEBU 1201ec5aa63SStefan Roese #define CONFIG_E1000 1211ec5aa63SStefan Roese #endif 1221ec5aa63SStefan Roese 123633fa0e7SStefan Roese #endif /* _CONFIG_MVEBU_ARMADA_8K_H */ 124