1 /* 2 * (C) Copyright 2010 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25 /* 26 * This file contains Marvell Board Specific common defincations. 27 * This file should be included in board config header file. 28 * 29 * It supports common definations for Kirkwood platform 30 * TBD: support for Orion5X platforms 31 */ 32 33 #ifndef _MV_COMMON_H 34 #define _MV_COMMON_H 35 36 /* 37 * High Level Configuration Options (easy to change) 38 */ 39 #define CONFIG_MARVELL 1 40 #define CONFIG_ARM926EJS 1 /* Basic Architecture */ 41 42 #if defined(CONFIG_KIRKWOOD) 43 #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ 44 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ 45 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ 46 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ 47 48 #define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE 49 #define MV_UART0_BASE KW_UART0_BASE 50 #define MV_SATA_BASE KW_SATA_BASE 51 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 52 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 53 54 #else 55 #error "Unsupported SoC" 56 #endif 57 58 /* 59 * CLKs configurations 60 */ 61 #define CONFIG_SYS_HZ 1000 62 63 /* 64 * NS16550 Configuration 65 */ 66 #define CONFIG_SYS_NS16550 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 70 #define CONFIG_SYS_NS16550_COM1 MV_UART0_BASE 71 72 /* 73 * Serial Port configuration 74 * The following definitions let you select what serial you want to use 75 * for your console driver. 76 */ 77 78 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 81 115200,230400, 460800, 921600 } 82 /* auto boot */ 83 #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ 84 85 /* 86 * For booting Linux, the board info and command line data 87 * have to be in the first 8 MB of memory, since this is 88 * the maximum mapped by the Linux kernel during initialization. 89 */ 90 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 91 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 92 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 93 94 #define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ 95 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 96 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 97 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 98 99 /* 100 * NAND configuration 101 */ 102 #ifdef CONFIG_CMD_NAND 103 #define CONFIG_NAND_KIRKWOOD 104 #define CONFIG_SYS_MAX_NAND_DEVICE 1 105 #define NAND_MAX_CHIPS 1 106 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 107 #define NAND_ALLOW_ERASE_ALL 1 108 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 109 #endif 110 111 /* 112 * SPI Flash configuration 113 */ 114 #ifdef CONFIG_CMD_SF 115 #define CONFIG_SPI_FLASH 1 116 #define CONFIG_HARD_SPI 1 117 #define CONFIG_KIRKWOOD_SPI 1 118 #define CONFIG_SPI_FLASH_MACRONIX 1 119 #define CONFIG_ENV_SPI_BUS 0 120 #define CONFIG_ENV_SPI_CS 0 121 #define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ 122 #endif 123 124 /* 125 * Size of malloc() pool 126 */ 127 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ 128 /* size in bytes reserved for initial data */ 129 #define CONFIG_SYS_GBL_DATA_SIZE 128 130 131 /* 132 * Other required minimal configurations 133 */ 134 #define CONFIG_SYS_LONGHELP 135 #define CONFIG_AUTO_COMPLETE 136 #define CONFIG_CMDLINE_EDITING 137 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 138 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 139 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 140 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 141 #define CONFIG_NR_DRAM_BANKS 4 142 #define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ 143 #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ 144 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ 145 #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ 146 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 147 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 148 149 /* 150 * Ethernet Driver configuration 151 */ 152 #ifdef CONFIG_CMD_NET 153 #define CONFIG_CMD_MII 154 #define CONFIG_NETCONSOLE /* include NetConsole support */ 155 #define CONFIG_NET_MULTI /* specify more that one ports available */ 156 #define CONFIG_MII /* expose smi ove miiphy interface */ 157 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ 158 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 159 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 160 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 161 #endif /* CONFIG_CMD_NET */ 162 163 /* 164 * USB/EHCI 165 */ 166 #ifdef CONFIG_CMD_USB 167 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 168 #define CONFIG_USB_EHCI_KIRKWOOD 169 #define CONFIG_EHCI_IS_TDI 170 #define CONFIG_USB_STORAGE 171 #define CONFIG_DOS_PARTITION 172 #define CONFIG_ISO_PARTITION 173 #define CONFIG_SUPPORT_VFAT 174 #endif /* CONFIG_CMD_USB */ 175 176 /* 177 * IDE Support on SATA ports 178 */ 179 #ifdef CONFIG_CMD_IDE 180 #define __io 181 #define CONFIG_CMD_EXT2 182 #define CONFIG_MVSATA_IDE 183 #define CONFIG_IDE_PREINIT 184 #define CONFIG_MVSATA_IDE_USE_PORT1 185 /* Needs byte-swapping for ATA data register */ 186 #define CONFIG_IDE_SWAP_IO 187 /* Data, registers and alternate blocks are at the same offset */ 188 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 189 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 190 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 191 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 192 #define CONFIG_SYS_ATA_STRIDE 4 193 /* Controller supports 48-bits LBA addressing */ 194 #define CONFIG_LBA48 195 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 196 #define CONFIG_SYS_IDE_MAXBUS 2 197 #define CONFIG_SYS_IDE_MAXDEVICE 2 198 /* ATA registers base is at SATA controller base */ 199 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE 200 #endif /* CONFIG_CMD_IDE */ 201 202 /* 203 * I2C related stuff 204 */ 205 #ifdef CONFIG_CMD_I2C 206 #define CONFIG_I2C_MVTWSI 207 #define CONFIG_SYS_I2C_SLAVE 0x0 208 #define CONFIG_SYS_I2C_SPEED 100000 209 #endif 210 211 /* 212 * File system 213 */ 214 #define CONFIG_CMD_EXT2 215 #define CONFIG_CMD_JFFS2 216 #define CONFIG_CMD_FAT 217 #define CONFIG_CMD_UBI 218 #define CONFIG_CMD_UBIFS 219 #define CONFIG_RBTREE 220 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 221 #define CONFIG_MTD_PARTITIONS 222 #define CONFIG_CMD_MTDPARTS 223 #define CONFIG_LZO 224 225 #endif /* _MV_COMMON_H */ 226