16c0bbdccSNobuhiro Iwamatsu /* 26c0bbdccSNobuhiro Iwamatsu * Configuation settings for the Hitachi Solution Engine 7722 36c0bbdccSNobuhiro Iwamatsu * 46c0bbdccSNobuhiro Iwamatsu * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 56c0bbdccSNobuhiro Iwamatsu * 66c0bbdccSNobuhiro Iwamatsu * See file CREDITS for list of people who contributed to this 76c0bbdccSNobuhiro Iwamatsu * project. 86c0bbdccSNobuhiro Iwamatsu * 96c0bbdccSNobuhiro Iwamatsu * This program is free software; you can redistribute it and/or 106c0bbdccSNobuhiro Iwamatsu * modify it under the terms of the GNU General Public License as 116c0bbdccSNobuhiro Iwamatsu * published by the Free Software Foundation; either version 2 of 126c0bbdccSNobuhiro Iwamatsu * the License, or (at your option) any later version. 136c0bbdccSNobuhiro Iwamatsu * 146c0bbdccSNobuhiro Iwamatsu * This program is distributed in the hope that it will be useful, 156c0bbdccSNobuhiro Iwamatsu * but WITHOUT ANY WARRANTY; without even the implied warranty of 166c0bbdccSNobuhiro Iwamatsu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 176c0bbdccSNobuhiro Iwamatsu * GNU General Public License for more details. 186c0bbdccSNobuhiro Iwamatsu * 196c0bbdccSNobuhiro Iwamatsu * You should have received a copy of the GNU General Public License 206c0bbdccSNobuhiro Iwamatsu * along with this program; if not, write to the Free Software 216c0bbdccSNobuhiro Iwamatsu * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 226c0bbdccSNobuhiro Iwamatsu * MA 02111-1307 USA 236c0bbdccSNobuhiro Iwamatsu */ 246c0bbdccSNobuhiro Iwamatsu 256c0bbdccSNobuhiro Iwamatsu #ifndef __MS7722SE_H 266c0bbdccSNobuhiro Iwamatsu #define __MS7722SE_H 276c0bbdccSNobuhiro Iwamatsu 286c0bbdccSNobuhiro Iwamatsu #define CONFIG_SH 1 296c0bbdccSNobuhiro Iwamatsu #define CONFIG_SH4 1 306c0bbdccSNobuhiro Iwamatsu #define CONFIG_CPU_SH7722 1 316c0bbdccSNobuhiro Iwamatsu #define CONFIG_MS7722SE 1 326c0bbdccSNobuhiro Iwamatsu 336c0bbdccSNobuhiro Iwamatsu #define CONFIG_CMD_FLASH 345783758fSNobuhiro Iwamatsu #define CONFIG_CMD_JFFS2 356c0bbdccSNobuhiro Iwamatsu #define CONFIG_CMD_NET 365783758fSNobuhiro Iwamatsu #define CONFIG_CMD_NFS 376c0bbdccSNobuhiro Iwamatsu #define CONFIG_CMD_PING 386c0bbdccSNobuhiro Iwamatsu #define CONFIG_CMD_DFL 396c0bbdccSNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM 405783758fSNobuhiro Iwamatsu #define CONFIG_CMD_MEMORY 41*bdab39d3SMike Frysinger #define CONFIG_CMD_SAVEENV 426c0bbdccSNobuhiro Iwamatsu 436c0bbdccSNobuhiro Iwamatsu #define CONFIG_BAUDRATE 115200 446c0bbdccSNobuhiro Iwamatsu #define CONFIG_BOOTDELAY 3 456c0bbdccSNobuhiro Iwamatsu #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" 466c0bbdccSNobuhiro Iwamatsu 476c0bbdccSNobuhiro Iwamatsu #define CONFIG_VERSION_VARIABLE 486c0bbdccSNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 496c0bbdccSNobuhiro Iwamatsu 506c0bbdccSNobuhiro Iwamatsu /* SMC9111 */ 516c0bbdccSNobuhiro Iwamatsu #define CONFIG_DRIVER_SMC91111 526c0bbdccSNobuhiro Iwamatsu #define CONFIG_SMC91111_BASE (0xB8000000) 536c0bbdccSNobuhiro Iwamatsu 546c0bbdccSNobuhiro Iwamatsu /* MEMORY */ 556c0bbdccSNobuhiro Iwamatsu #define MS7722SE_SDRAM_BASE (0x8C000000) 566c0bbdccSNobuhiro Iwamatsu #define MS7722SE_FLASH_BASE_1 (0xA0000000) 576c0bbdccSNobuhiro Iwamatsu #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) 586c0bbdccSNobuhiro Iwamatsu 596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 666c0bbdccSNobuhiro Iwamatsu 676c0bbdccSNobuhiro Iwamatsu /* SCIF */ 686c58a030SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SCIF_CONSOLE 1 696c0bbdccSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0 1 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */ 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 736c0bbdccSNobuhiro Iwamatsu 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE) 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 766c0bbdccSNobuhiro Iwamatsu 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */ 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ 796c0bbdccSNobuhiro Iwamatsu 806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ 816c0bbdccSNobuhiro Iwamatsu 826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE) 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ 846c0bbdccSNobuhiro Iwamatsu 856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ 866c0bbdccSNobuhiro Iwamatsu 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image 886c0bbdccSNobuhiro Iwamatsu in Flash (NOT run time address in SDRAM) ?!? */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */ 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE (256) /* size in bytes reserved for initial data */ 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 936c0bbdccSNobuhiro Iwamatsu 946c0bbdccSNobuhiro Iwamatsu /* FLASH */ 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 9600b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_QUIET_TEST 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 996c0bbdccSNobuhiro Iwamatsu 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ 1016c0bbdccSNobuhiro Iwamatsu 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each 1036c0bbdccSNobuhiro Iwamatsu Flash chip */ 1046c0bbdccSNobuhiro Iwamatsu 1056c0bbdccSNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ 1096c0bbdccSNobuhiro Iwamatsu } 1106c0bbdccSNobuhiro Iwamatsu 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ 1156c0bbdccSNobuhiro Iwamatsu 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */ 1176c0bbdccSNobuhiro Iwamatsu 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_DIRECT_FLASH_TFTP 1196c0bbdccSNobuhiro Iwamatsu 1205a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1216c0bbdccSNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 1220e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (8 * 1024) 1230e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 1260e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 1286c0bbdccSNobuhiro Iwamatsu 1296c0bbdccSNobuhiro Iwamatsu /* Board Clock */ 1306c0bbdccSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 33333333 1316c0bbdccSNobuhiro Iwamatsu #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) 1336c0bbdccSNobuhiro Iwamatsu 1346c0bbdccSNobuhiro Iwamatsu #endif /* __MS7722SE_H */ 135