1 /* 2 * Configuation settings for the Hitachi Solution Engine 7720 3 * 4 * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MS7720SE_H 10 #define __MS7720SE_H 11 12 #define CONFIG_CPU_SH7720 1 13 #define CONFIG_MS7720SE 1 14 15 #define CONFIG_BOOTFILE "/boot/zImage" 16 #define CONFIG_LOADADDR 0x8E000000 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 #undef CONFIG_SHOW_BOOT_PROGRESS 20 21 /* MEMORY */ 22 #define MS7720SE_SDRAM_BASE 0x8C000000 23 #define MS7720SE_FLASH_BASE_1 0xA0000000 24 #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) 25 26 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 27 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 28 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 29 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 30 /* Buffer size for Boot Arguments passed to kernel */ 31 #define CONFIG_SYS_BARGSIZE 512 32 /* List of legal baudrate settings for this board */ 33 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 34 35 /* SCIF */ 36 #define CONFIG_CONS_SCIF0 1 37 38 #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE 39 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 40 41 #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE 42 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 43 44 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 45 #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 46 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 47 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 48 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 49 50 /* FLASH */ 51 #define CONFIG_SYS_FLASH_CFI 52 #define CONFIG_FLASH_CFI_DRIVER 53 #undef CONFIG_SYS_FLASH_QUIET_TEST 54 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 55 56 #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 57 58 #define CONFIG_SYS_MAX_FLASH_SECT 150 59 #define CONFIG_SYS_MAX_FLASH_BANKS 1 60 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 61 62 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 63 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 64 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 65 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 66 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 67 68 /* Board Clock */ 69 #define CONFIG_SYS_CLK_FREQ 33333333 70 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 71 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ 73 74 /* PCMCIA */ 75 #define CONFIG_IDE_PCMCIA 1 76 #define CONFIG_MARUBUN_PCCARD 1 77 #define CONFIG_PCMCIA_SLOT_A 1 78 #define CONFIG_SYS_IDE_MAXDEVICE 1 79 #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 80 #define CONFIG_SYS_MARUBUN_MW1 0xb8400000 81 #define CONFIG_SYS_MARUBUN_MW2 0xb8500000 82 #define CONFIG_SYS_MARUBUN_IO 0xb8600000 83 84 #define CONFIG_SYS_PIO_MODE 1 85 #define CONFIG_SYS_IDE_MAXBUS 1 86 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ 87 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 88 #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 89 #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 90 #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 91 #define CONFIG_IDE_SWAP_IO 92 93 #endif /* __MS7720SE_H */ 94