1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc. 19 */ 20 21 #ifndef __CONFIG_H 22 #define __CONFIG_H 23 24 /* 25 * High Level Configuration Options 26 */ 27 #define CONFIG_OMAP /* in a TI OMAP core */ 28 #define CONFIG_OMAP34XX /* which is a 34XX */ 29 #define CONFIG_OMAP3_MCX /* working with mcx */ 30 31 #define MACH_TYPE_MCX 3656 32 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 33 34 #define CONFIG_SYS_CACHELINE_SIZE 64 35 36 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 37 38 #include <asm/arch/cpu.h> /* get chip and board defs */ 39 #include <asm/arch/omap3.h> 40 41 #define CONFIG_OF_LIBFDT 42 #define CONFIG_FIT 43 44 /* 45 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 46 * and older u-boot.bin with the new U-Boot SPL. 47 */ 48 #define CONFIG_SYS_TEXT_BASE 0x80008000 49 50 /* 51 * Display CPU and Board information 52 */ 53 #define CONFIG_DISPLAY_CPUINFO 54 #define CONFIG_DISPLAY_BOARDINFO 55 56 /* Clock Defines */ 57 #define V_OSCK 26000000 /* Clock output from T2 */ 58 #define V_SCLK (V_OSCK >> 1) 59 60 #define CONFIG_MISC_INIT_R 61 62 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 63 #define CONFIG_SETUP_MEMORY_TAGS 64 #define CONFIG_INITRD_TAG 65 #define CONFIG_REVISION_TAG 66 67 /* 68 * Size of malloc() pool 69 */ 70 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 71 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 72 /* 73 * DDR related 74 */ 75 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 76 77 /* 78 * Hardware drivers 79 */ 80 81 /* 82 * NS16550 Configuration 83 */ 84 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 85 86 #define CONFIG_SYS_NS16550 87 #define CONFIG_SYS_NS16550_SERIAL 88 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 89 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 90 91 /* 92 * select serial console configuration 93 */ 94 #define CONFIG_CONS_INDEX 3 95 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 96 #define CONFIG_SERIAL3 3 /* UART3 */ 97 98 /* allow to overwrite serial and ethaddr */ 99 #define CONFIG_ENV_OVERWRITE 100 #define CONFIG_BAUDRATE 115200 101 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 102 115200} 103 #define CONFIG_MMC 104 #define CONFIG_OMAP_HSMMC 105 #define CONFIG_GENERIC_MMC 106 #define CONFIG_DOS_PARTITION 107 108 /* EHCI */ 109 #define CONFIG_USB_STORAGE 110 #define CONFIG_OMAP3_GPIO_5 111 #define CONFIG_USB_EHCI 112 #define CONFIG_USB_EHCI_OMAP 113 #define CONFIG_USB_ULPI 114 #define CONFIG_USB_ULPI_VIEWPORT_OMAP 115 /*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ 116 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 117 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 118 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 119 120 /* commands to include */ 121 #include <config_cmd_default.h> 122 123 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 124 #define CONFIG_CMD_FAT /* FAT support */ 125 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 126 127 #define CONFIG_CMD_DATE 128 #define CONFIG_CMD_I2C /* I2C serial bus support */ 129 #define CONFIG_CMD_MMC /* MMC support */ 130 #define CONFIG_CMD_FAT /* FAT support */ 131 #define CONFIG_CMD_USB 132 #define CONFIG_CMD_NAND /* NAND support */ 133 #define CONFIG_CMD_DHCP 134 #define CONFIG_CMD_PING 135 #define CONFIG_CMD_CACHE 136 #define CONFIG_CMD_UBI 137 #define CONFIG_CMD_UBIFS 138 #define CONFIG_RBTREE 139 #define CONFIG_LZO 140 #define CONFIG_MTD_PARTITIONS 141 #define CONFIG_MTD_DEVICE 142 #define CONFIG_CMD_MTDPARTS 143 144 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 145 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 146 #undef CONFIG_CMD_IMI /* iminfo */ 147 #undef CONFIG_CMD_IMLS /* List all found images */ 148 149 #define CONFIG_SYS_NO_FLASH 150 #define CONFIG_HARD_I2C 151 #define CONFIG_SYS_I2C_SPEED 100000 152 #define CONFIG_SYS_I2C_SLAVE 1 153 #define CONFIG_SYS_I2C_BUS 0 154 #define CONFIG_DRIVER_OMAP34XX_I2C 155 156 /* RTC */ 157 #define CONFIG_RTC_DS1337 158 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 159 160 #define CONFIG_CMD_NET 161 #define CONFIG_CMD_MII 162 #define CONFIG_CMD_NFS 163 /* 164 * Board NAND Info. 165 */ 166 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 167 /* to access nand */ 168 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 169 /* to access */ 170 /* nand at CS0 */ 171 172 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 173 /* NAND devices */ 174 #define CONFIG_JFFS2_NAND 175 /* nand device jffs2 lives on */ 176 #define CONFIG_JFFS2_DEV "nand0" 177 /* start of jffs2 partition */ 178 #define CONFIG_JFFS2_PART_OFFSET 0x680000 179 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 180 181 /* Environment information */ 182 #define CONFIG_BOOTDELAY 10 183 184 #define CONFIG_BOOTFILE "uImage" 185 186 #define xstr(s) str(s) 187 #define str(s) #s 188 189 /* Setup MTD for NAND on the SOM */ 190 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 191 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 192 "1m(u-boot),256k(env1)," \ 193 "256k(env2),6m(kernel),6m(k_recovery)," \ 194 "8m(fs_recovery),-(common_data)" 195 196 #define CONFIG_HOSTNAME mcx 197 #define CONFIG_EXTRA_ENV_SETTINGS \ 198 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 199 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 200 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 201 "addfb=setenv bootargs ${bootargs} vram=6M " \ 202 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 203 "addip_sta=setenv bootargs ${bootargs} " \ 204 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 205 "${netmask}:${hostname}:eth0:off\0" \ 206 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 207 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 208 "else run addip_sta;fi\0" \ 209 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 210 "addtty=setenv bootargs ${bootargs} " \ 211 "console=${consoledev},${baudrate}\0" \ 212 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 213 "baudrate=115200\0" \ 214 "consoledev=ttyO2\0" \ 215 "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ 216 "loadaddr=0x82000000\0" \ 217 "load=tftp ${loadaddr} ${u-boot}\0" \ 218 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 219 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 220 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 221 "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ 222 "mmcargs=root=/dev/mmcblk0p2 rw " \ 223 "rootfstype=ext3 rootwait\0" \ 224 "mmcboot=echo Booting from mmc ...; " \ 225 "run mmcargs; " \ 226 "run addip addtty addmtd addfb addeth addmisc;" \ 227 "run loaduimage; " \ 228 "bootm ${loadaddr}\0" \ 229 "net_nfs=run load_k; " \ 230 "run nfsargs; " \ 231 "run addip addtty addmtd addfb addeth addmisc;" \ 232 "bootm ${loadaddr}\0" \ 233 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 234 "nfsroot=${serverip}:${rootpath}\0" \ 235 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ 236 "uboot_addr=0x80000\0" \ 237 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 238 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 239 "updatemlo=nandecc hw;nand erase 0 20000;" \ 240 "nand write ${loadaddr} 0 20000\0" \ 241 "upd=if run load;then echo Updating u-boot;if run update;" \ 242 "then echo U-Boot updated;" \ 243 "else echo Error updating u-boot !;" \ 244 "echo Board without bootloader !!;" \ 245 "fi;" \ 246 "else echo U-Boot not downloaded..exiting;fi\0" \ 247 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 248 "bootscript=echo Running bootscript from mmc ...; " \ 249 "source ${loadaddr}\0" \ 250 "nandargs=setenv bootargs ubi.mtd=7 " \ 251 "root=ubi0:rootfs rootfstype=ubifs\0" \ 252 "nandboot=echo Booting from nand ...; " \ 253 "run nandargs; " \ 254 "ubi part nand0,4;" \ 255 "ubi readvol ${loadaddr} kernel;" \ 256 "run addip addtty addmtd addfb addeth addmisc;" \ 257 "bootm ${loadaddr}\0" \ 258 "swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\ 259 "rootfstype=ubifs quiet loglevel=1 " \ 260 "consoleblank=0 ${swupdate_misc}\0" \ 261 "swupdate=echo Running Sw-Update...;" \ 262 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 263 "else mtdparts default;fi; " \ 264 "ubi part nand0,5;" \ 265 "ubi readvol 0x82000000 kernel_recovery;" \ 266 "run swupdate_args; " \ 267 "setenv bootargs ${bootargs} " \ 268 "${mtdparts} " \ 269 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 270 "omapdss.def_disp=lcd;" \ 271 "bootm ${loadaddr}\0" 272 273 #define CONFIG_BOOTCOMMAND \ 274 "run nandboot" 275 276 #define CONFIG_AUTO_COMPLETE 277 #define CONFIG_CMDLINE_EDITING 278 279 /* 280 * Miscellaneous configurable options 281 */ 282 #define V_PROMPT "mcx # " 283 284 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 285 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 286 #define CONFIG_SYS_PROMPT V_PROMPT 287 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 288 /* Print Buffer Size */ 289 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 290 sizeof(CONFIG_SYS_PROMPT) + 16) 291 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 292 /* args */ 293 /* Boot Argument Buffer Size */ 294 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 295 /* memtest works on */ 296 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 297 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 298 0x01F00000) /* 31MB */ 299 300 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 301 /* address */ 302 303 /* 304 * AM3517 has 12 GP timers, they can be driven by the system clock 305 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 306 * This rate is divided by a local divisor. 307 */ 308 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 309 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 310 #define CONFIG_SYS_HZ 1000 311 312 /* 313 * Stack sizes 314 * 315 * The stack sizes are set up in start.S using the settings below 316 */ 317 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 318 319 /* 320 * Physical Memory Map 321 */ 322 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 323 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 324 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 325 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 326 327 /* 328 * FLASH and environment organization 329 */ 330 331 /* **** PISMO SUPPORT *** */ 332 333 /* Configure the PISMO */ 334 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 335 336 #define CONFIG_NAND_OMAP_GPMC 337 #define GPMC_NAND_ECC_LP_x16_LAYOUT 338 #define CONFIG_ENV_IS_IN_NAND 339 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 340 341 /* Redundant Environment */ 342 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 343 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 344 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 345 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 346 2 * CONFIG_SYS_ENV_SECT_SIZE) 347 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 348 349 /* Flash banks JFFS2 should use */ 350 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 351 CONFIG_SYS_MAX_NAND_DEVICE) 352 #define CONFIG_SYS_JFFS2_MEM_NAND 353 /* use flash_info[2] */ 354 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 355 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 356 357 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 358 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 359 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 360 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 361 CONFIG_SYS_INIT_RAM_SIZE - \ 362 GENERATED_GBL_DATA_SIZE) 363 364 /* Defines for SPL */ 365 #define CONFIG_SPL 366 #define CONFIG_SPL_NAND_SIMPLE 367 #define CONFIG_SPL_NAND_SOFTECC 368 369 #define CONFIG_SPL_LIBCOMMON_SUPPORT 370 #define CONFIG_SPL_LIBDISK_SUPPORT 371 #define CONFIG_SPL_I2C_SUPPORT 372 #define CONFIG_SPL_MMC_SUPPORT 373 #define CONFIG_SPL_FAT_SUPPORT 374 #define CONFIG_SPL_LIBGENERIC_SUPPORT 375 #define CONFIG_SPL_SERIAL_SUPPORT 376 #define CONFIG_SPL_POWER_SUPPORT 377 #define CONFIG_SPL_NAND_SUPPORT 378 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 379 380 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 381 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 382 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 383 384 /* move malloc and bss high to prevent clashing with the main image */ 385 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 386 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 387 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 388 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 389 390 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 391 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 392 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 393 394 /* NAND boot config */ 395 #define CONFIG_SYS_NAND_PAGE_COUNT 64 396 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 397 #define CONFIG_SYS_NAND_OOBSIZE 64 398 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 399 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 400 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 401 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 402 48, 49, 50, 51, 52, 53, 54, 55,\ 403 56, 57, 58, 59, 60, 61, 62, 63} 404 #define CONFIG_SYS_NAND_ECCSIZE 256 405 #define CONFIG_SYS_NAND_ECCBYTES 3 406 407 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 408 409 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 410 411 /* 412 * ethernet support 413 * 414 */ 415 #if defined(CONFIG_CMD_NET) 416 #define CONFIG_DRIVER_TI_EMAC 417 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 418 #define CONFIG_MII 419 #define CONFIG_BOOTP_DEFAULT 420 #define CONFIG_BOOTP_DNS 421 #define CONFIG_BOOTP_DNS2 422 #define CONFIG_BOOTP_SEND_HOSTNAME 423 #define CONFIG_NET_RETRY_COUNT 10 424 #endif 425 426 #endif /* __CONFIG_H */ 427