1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define MACH_TYPE_MCX 3656 25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 26 #define CONFIG_BOARD_LATE_INIT 27 28 #define CONFIG_SYS_CACHELINE_SIZE 64 29 30 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap.h> 34 35 /* 36 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 37 * and older u-boot.bin with the new U-Boot SPL. 38 */ 39 #define CONFIG_SYS_TEXT_BASE 0x80008000 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 /* Clock Defines */ 48 #define V_OSCK 26000000 /* Clock output from T2 */ 49 #define V_SCLK (V_OSCK >> 1) 50 51 #define CONFIG_MISC_INIT_R 52 53 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 54 #define CONFIG_SETUP_MEMORY_TAGS 55 #define CONFIG_INITRD_TAG 56 #define CONFIG_REVISION_TAG 57 58 /* 59 * Size of malloc() pool 60 */ 61 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 63 /* 64 * DDR related 65 */ 66 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 67 68 /* 69 * Hardware drivers 70 */ 71 72 /* 73 * NS16550 Configuration 74 */ 75 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 76 77 #define CONFIG_SYS_NS16550_SERIAL 78 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 79 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 80 81 /* 82 * select serial console configuration 83 */ 84 #define CONFIG_CONS_INDEX 3 85 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 86 #define CONFIG_SERIAL3 3 /* UART3 */ 87 88 /* allow to overwrite serial and ethaddr */ 89 #define CONFIG_ENV_OVERWRITE 90 #define CONFIG_BAUDRATE 115200 91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 92 115200} 93 #define CONFIG_MMC 94 #define CONFIG_OMAP_HSMMC 95 #define CONFIG_GENERIC_MMC 96 #define CONFIG_DOS_PARTITION 97 98 /* EHCI */ 99 #define CONFIG_USB_STORAGE 100 #define CONFIG_OMAP3_GPIO_2 101 #define CONFIG_OMAP3_GPIO_5 102 #define CONFIG_USB_EHCI 103 #define CONFIG_USB_EHCI_OMAP 104 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 105 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 106 #define CONFIG_USB_HOST_ETHER 107 #define CONFIG_USB_ETHER_ASIX 108 #define CONFIG_USB_ETHER_MCS7830 109 110 /* commands to include */ 111 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 112 #define CONFIG_CMD_FAT /* FAT support */ 113 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 114 115 #define CONFIG_CMD_DATE 116 #define CONFIG_CMD_MMC /* MMC support */ 117 #define CONFIG_CMD_FAT /* FAT support */ 118 #define CONFIG_CMD_NAND /* NAND support */ 119 #define CONFIG_CMD_CACHE 120 #define CONFIG_CMD_UBI 121 #define CONFIG_CMD_UBIFS 122 #define CONFIG_RBTREE 123 #define CONFIG_LZO 124 #define CONFIG_MTD_PARTITIONS 125 #define CONFIG_MTD_DEVICE 126 #define CONFIG_CMD_MTDPARTS 127 128 #define CONFIG_SYS_NO_FLASH 129 #define CONFIG_SYS_I2C 130 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 131 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 132 #define CONFIG_SYS_I2C_OMAP34XX 133 134 /* RTC */ 135 #define CONFIG_RTC_DS1337 136 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 137 138 #define CONFIG_CMD_MII 139 /* 140 * Board NAND Info. 141 */ 142 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 143 /* to access nand */ 144 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 145 /* to access */ 146 /* nand at CS0 */ 147 148 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 149 /* NAND devices */ 150 #define CONFIG_JFFS2_NAND 151 /* nand device jffs2 lives on */ 152 #define CONFIG_JFFS2_DEV "nand0" 153 /* start of jffs2 partition */ 154 #define CONFIG_JFFS2_PART_OFFSET 0x680000 155 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 156 157 /* Environment information */ 158 #define CONFIG_BOOTDELAY 3 159 160 #define CONFIG_BOOTFILE "uImage" 161 162 /* Setup MTD for NAND on the SOM */ 163 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 164 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 165 "1m(u-boot),256k(env1)," \ 166 "256k(env2),6m(kernel),6m(k_recovery)," \ 167 "8m(fs_recovery),-(common_data)" 168 169 #define CONFIG_HOSTNAME mcx 170 #define CONFIG_EXTRA_ENV_SETTINGS \ 171 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 172 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 173 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 174 "addfb=setenv bootargs ${bootargs} vram=6M " \ 175 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 176 "addip_sta=setenv bootargs ${bootargs} " \ 177 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 178 "${netmask}:${hostname}:eth0:off\0" \ 179 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 180 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 181 "else run addip_sta;fi\0" \ 182 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 183 "addtty=setenv bootargs ${bootargs} " \ 184 "console=${consoledev},${baudrate}\0" \ 185 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 186 "baudrate=115200\0" \ 187 "consoledev=ttyO2\0" \ 188 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 189 "loadaddr=0x82000000\0" \ 190 "load=tftp ${loadaddr} ${u-boot}\0" \ 191 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 192 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 193 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 194 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 195 "mmcargs=root=/dev/mmcblk0p2 rw " \ 196 "rootfstype=ext3 rootwait\0" \ 197 "mmcboot=echo Booting from mmc ...; " \ 198 "run mmcargs; " \ 199 "run addip addtty addmtd addfb addeth addmisc;" \ 200 "run loaduimage; " \ 201 "bootm ${loadaddr}\0" \ 202 "net_nfs=run load_k; " \ 203 "run nfsargs; " \ 204 "run addip addtty addmtd addfb addeth addmisc;" \ 205 "bootm ${loadaddr}\0" \ 206 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 207 "nfsroot=${serverip}:${rootpath}\0" \ 208 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 209 "uboot_addr=0x80000\0" \ 210 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 211 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 212 "updatemlo=nandecc hw;nand erase 0 20000;" \ 213 "nand write ${loadaddr} 0 20000\0" \ 214 "upd=if run load;then echo Updating u-boot;if run update;" \ 215 "then echo U-Boot updated;" \ 216 "else echo Error updating u-boot !;" \ 217 "echo Board without bootloader !!;" \ 218 "fi;" \ 219 "else echo U-Boot not downloaded..exiting;fi\0" \ 220 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 221 "bootscript=echo Running bootscript from mmc ...; " \ 222 "source ${loadaddr}\0" \ 223 "nandargs=setenv bootargs ubi.mtd=7 " \ 224 "root=ubi0:rootfs rootfstype=ubifs\0" \ 225 "nandboot=echo Booting from nand ...; " \ 226 "run nandargs; " \ 227 "ubi part nand0,4;" \ 228 "ubi readvol ${loadaddr} kernel;" \ 229 "run addtty addmtd addfb addeth addmisc;" \ 230 "bootm ${loadaddr}\0" \ 231 "preboot=ubi part nand0,7;" \ 232 "ubi readvol ${loadaddr} splash;" \ 233 "bmp display ${loadaddr};" \ 234 "gpio set 55\0" \ 235 "swupdate_args=setenv bootargs root=/dev/ram " \ 236 "quiet loglevel=1 " \ 237 "consoleblank=0 ${swupdate_misc}\0" \ 238 "swupdate=echo Running Sw-Update...;" \ 239 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 240 "else mtdparts default;fi; " \ 241 "ubi part nand0,5;" \ 242 "ubi readvol 0x82000000 kernel_recovery;" \ 243 "ubi part nand0,6;" \ 244 "ubi readvol 0x84000000 fs_recovery;" \ 245 "run swupdate_args; " \ 246 "setenv bootargs ${bootargs} " \ 247 "${mtdparts} " \ 248 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 249 "omapdss.def_disp=lcd;" \ 250 "bootm 0x82000000 0x84000000\0" \ 251 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 252 "then source 82000000;else run nandboot;fi\0" 253 254 #define CONFIG_AUTO_COMPLETE 255 #define CONFIG_CMDLINE_EDITING 256 257 /* 258 * Miscellaneous configurable options 259 */ 260 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 261 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 262 /* Print Buffer Size */ 263 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 264 sizeof(CONFIG_SYS_PROMPT) + 16) 265 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 266 /* args */ 267 /* Boot Argument Buffer Size */ 268 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 269 /* memtest works on */ 270 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 271 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 272 0x01F00000) /* 31MB */ 273 274 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 275 /* address */ 276 #define CONFIG_PREBOOT 277 278 /* 279 * AM3517 has 12 GP timers, they can be driven by the system clock 280 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 281 * This rate is divided by a local divisor. 282 */ 283 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 284 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 285 286 /* 287 * Physical Memory Map 288 */ 289 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 290 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 291 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 292 293 /* 294 * FLASH and environment organization 295 */ 296 297 /* **** PISMO SUPPORT *** */ 298 #define CONFIG_NAND 299 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 300 #define CONFIG_NAND_OMAP_GPMC 301 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 302 #define CONFIG_ENV_IS_IN_NAND 303 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 304 305 /* Redundant Environment */ 306 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 307 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 308 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 309 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 310 2 * CONFIG_SYS_ENV_SECT_SIZE) 311 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 312 313 /* Flash banks JFFS2 should use */ 314 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 315 CONFIG_SYS_MAX_NAND_DEVICE) 316 #define CONFIG_SYS_JFFS2_MEM_NAND 317 /* use flash_info[2] */ 318 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 319 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 320 321 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 322 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 323 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 324 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 325 CONFIG_SYS_INIT_RAM_SIZE - \ 326 GENERATED_GBL_DATA_SIZE) 327 328 /* Defines for SPL */ 329 #define CONFIG_SPL_FRAMEWORK 330 #define CONFIG_SPL_BOARD_INIT 331 #define CONFIG_SPL_NAND_SIMPLE 332 333 #define CONFIG_SPL_LIBCOMMON_SUPPORT 334 #define CONFIG_SPL_LIBDISK_SUPPORT 335 #define CONFIG_SPL_I2C_SUPPORT 336 #define CONFIG_SPL_MMC_SUPPORT 337 #define CONFIG_SPL_FAT_SUPPORT 338 #define CONFIG_SPL_LIBGENERIC_SUPPORT 339 #define CONFIG_SPL_SERIAL_SUPPORT 340 #define CONFIG_SPL_POWER_SUPPORT 341 #define CONFIG_SPL_NAND_SUPPORT 342 #define CONFIG_SPL_NAND_BASE 343 #define CONFIG_SPL_NAND_DRIVERS 344 #define CONFIG_SPL_NAND_ECC 345 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 346 347 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 348 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 349 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 350 351 /* move malloc and bss high to prevent clashing with the main image */ 352 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 353 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 354 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 355 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 356 357 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 358 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 359 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 360 361 /* NAND boot config */ 362 #define CONFIG_SYS_NAND_PAGE_COUNT 64 363 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 364 #define CONFIG_SYS_NAND_OOBSIZE 64 365 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 366 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 367 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 368 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 369 48, 49, 50, 51, 52, 53, 54, 55,\ 370 56, 57, 58, 59, 60, 61, 62, 63} 371 #define CONFIG_SYS_NAND_ECCSIZE 256 372 #define CONFIG_SYS_NAND_ECCBYTES 3 373 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 374 #define CONFIG_SPL_NAND_SOFTECC 375 376 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 377 378 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 379 380 /* 381 * ethernet support 382 * 383 */ 384 #if defined(CONFIG_CMD_NET) 385 #define CONFIG_DRIVER_TI_EMAC 386 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 387 #define CONFIG_MII 388 #define CONFIG_BOOTP_DNS 389 #define CONFIG_BOOTP_DNS2 390 #define CONFIG_BOOTP_SEND_HOSTNAME 391 #define CONFIG_NET_RETRY_COUNT 10 392 #endif 393 394 #define CONFIG_VIDEO 395 #define CONFIG_CFB_CONSOLE 396 #define CONFIG_VGA_AS_SINGLE_DEVICE 397 #define CONFIG_SPLASH_SCREEN 398 #define CONFIG_VIDEO_BMP_RLE8 399 #define CONFIG_CMD_BMP 400 #define CONFIG_VIDEO_OMAP3 401 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 402 403 #endif /* __CONFIG_H */ 404