1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP_GPIO 16 17 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 18 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* 25 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 26 * and older u-boot.bin with the new U-Boot SPL. 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0x80008000 29 30 /* Clock Defines */ 31 #define V_OSCK 26000000 /* Clock output from T2 */ 32 #define V_SCLK (V_OSCK >> 1) 33 34 #define CONFIG_MISC_INIT_R 35 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_REVISION_TAG 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 45 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 46 /* 47 * DDR related 48 */ 49 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 50 51 /* 52 * Hardware drivers 53 */ 54 55 /* 56 * NS16550 Configuration 57 */ 58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 59 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 63 64 /* 65 * select serial console configuration 66 */ 67 #define CONFIG_CONS_INDEX 3 68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 69 #define CONFIG_SERIAL3 3 /* UART3 */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 74 115200} 75 76 /* EHCI */ 77 #define CONFIG_OMAP3_GPIO_2 78 #define CONFIG_OMAP3_GPIO_5 79 #define CONFIG_USB_EHCI 80 #define CONFIG_USB_EHCI_OMAP 81 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 82 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 83 #define CONFIG_USB_HOST_ETHER 84 #define CONFIG_USB_ETHER_ASIX 85 #define CONFIG_USB_ETHER_MCS7830 86 87 /* commands to include */ 88 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 89 90 #define CONFIG_CMD_NAND /* NAND support */ 91 #define CONFIG_CMD_UBIFS 92 #define CONFIG_RBTREE 93 #define CONFIG_LZO 94 #define CONFIG_MTD_PARTITIONS 95 #define CONFIG_MTD_DEVICE 96 #define CONFIG_CMD_MTDPARTS 97 98 #define CONFIG_SYS_I2C 99 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 100 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 101 #define CONFIG_SYS_I2C_OMAP34XX 102 103 /* RTC */ 104 #define CONFIG_RTC_DS1337 105 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 106 107 /* 108 * Board NAND Info. 109 */ 110 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 111 /* to access nand */ 112 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 113 /* to access */ 114 /* nand at CS0 */ 115 116 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 117 /* NAND devices */ 118 #define CONFIG_JFFS2_NAND 119 /* nand device jffs2 lives on */ 120 #define CONFIG_JFFS2_DEV "nand0" 121 /* start of jffs2 partition */ 122 #define CONFIG_JFFS2_PART_OFFSET 0x680000 123 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 124 125 /* Environment information */ 126 127 #define CONFIG_BOOTFILE "uImage" 128 129 /* Setup MTD for NAND on the SOM */ 130 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 131 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 132 "1m(u-boot),256k(env1)," \ 133 "256k(env2),6m(kernel),6m(k_recovery)," \ 134 "8m(fs_recovery),-(common_data)" 135 136 #define CONFIG_HOSTNAME mcx 137 #define CONFIG_EXTRA_ENV_SETTINGS \ 138 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 139 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 140 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 141 "addfb=setenv bootargs ${bootargs} vram=6M " \ 142 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 143 "addip_sta=setenv bootargs ${bootargs} " \ 144 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 145 "${netmask}:${hostname}:eth0:off\0" \ 146 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 147 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 148 "else run addip_sta;fi\0" \ 149 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 150 "addtty=setenv bootargs ${bootargs} " \ 151 "console=${consoledev},${baudrate}\0" \ 152 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 153 "baudrate=115200\0" \ 154 "consoledev=ttyO2\0" \ 155 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 156 "loadaddr=0x82000000\0" \ 157 "load=tftp ${loadaddr} ${u-boot}\0" \ 158 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 159 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 160 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 161 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 162 "mmcargs=root=/dev/mmcblk0p2 rw " \ 163 "rootfstype=ext3 rootwait\0" \ 164 "mmcboot=echo Booting from mmc ...; " \ 165 "run mmcargs; " \ 166 "run addip addtty addmtd addfb addeth addmisc;" \ 167 "run loaduimage; " \ 168 "bootm ${loadaddr}\0" \ 169 "net_nfs=run load_k; " \ 170 "run nfsargs; " \ 171 "run addip addtty addmtd addfb addeth addmisc;" \ 172 "bootm ${loadaddr}\0" \ 173 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 174 "nfsroot=${serverip}:${rootpath}\0" \ 175 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 176 "uboot_addr=0x80000\0" \ 177 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 178 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 179 "updatemlo=nandecc hw;nand erase 0 20000;" \ 180 "nand write ${loadaddr} 0 20000\0" \ 181 "upd=if run load;then echo Updating u-boot;if run update;" \ 182 "then echo U-Boot updated;" \ 183 "else echo Error updating u-boot !;" \ 184 "echo Board without bootloader !!;" \ 185 "fi;" \ 186 "else echo U-Boot not downloaded..exiting;fi\0" \ 187 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 188 "bootscript=echo Running bootscript from mmc ...; " \ 189 "source ${loadaddr}\0" \ 190 "nandargs=setenv bootargs ubi.mtd=7 " \ 191 "root=ubi0:rootfs rootfstype=ubifs\0" \ 192 "nandboot=echo Booting from nand ...; " \ 193 "run nandargs; " \ 194 "ubi part nand0,4;" \ 195 "ubi readvol ${loadaddr} kernel;" \ 196 "run addtty addmtd addfb addeth addmisc;" \ 197 "bootm ${loadaddr}\0" \ 198 "preboot=ubi part nand0,7;" \ 199 "ubi readvol ${loadaddr} splash;" \ 200 "bmp display ${loadaddr};" \ 201 "gpio set 55\0" \ 202 "swupdate_args=setenv bootargs root=/dev/ram " \ 203 "quiet loglevel=1 " \ 204 "consoleblank=0 ${swupdate_misc}\0" \ 205 "swupdate=echo Running Sw-Update...;" \ 206 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 207 "else mtdparts default;fi; " \ 208 "ubi part nand0,5;" \ 209 "ubi readvol 0x82000000 kernel_recovery;" \ 210 "ubi part nand0,6;" \ 211 "ubi readvol 0x84000000 fs_recovery;" \ 212 "run swupdate_args; " \ 213 "setenv bootargs ${bootargs} " \ 214 "${mtdparts} " \ 215 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 216 "omapdss.def_disp=lcd;" \ 217 "bootm 0x82000000 0x84000000\0" \ 218 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 219 "then source 82000000;else run nandboot;fi\0" 220 221 #define CONFIG_AUTO_COMPLETE 222 #define CONFIG_CMDLINE_EDITING 223 224 /* 225 * Miscellaneous configurable options 226 */ 227 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 228 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 229 /* Print Buffer Size */ 230 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 231 sizeof(CONFIG_SYS_PROMPT) + 16) 232 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 233 /* args */ 234 /* Boot Argument Buffer Size */ 235 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 236 /* memtest works on */ 237 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 238 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 239 0x01F00000) /* 31MB */ 240 241 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 242 /* address */ 243 #define CONFIG_PREBOOT 244 245 /* 246 * AM3517 has 12 GP timers, they can be driven by the system clock 247 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 248 * This rate is divided by a local divisor. 249 */ 250 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 251 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 252 253 /* 254 * Physical Memory Map 255 */ 256 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 257 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 258 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 259 260 /* 261 * FLASH and environment organization 262 */ 263 264 /* **** PISMO SUPPORT *** */ 265 #define CONFIG_NAND 266 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 267 #define CONFIG_NAND_OMAP_GPMC 268 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 269 #define CONFIG_ENV_IS_IN_NAND 270 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 271 272 /* Redundant Environment */ 273 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 274 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 275 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 276 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 277 2 * CONFIG_SYS_ENV_SECT_SIZE) 278 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 279 280 /* Flash banks JFFS2 should use */ 281 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 282 CONFIG_SYS_MAX_NAND_DEVICE) 283 #define CONFIG_SYS_JFFS2_MEM_NAND 284 /* use flash_info[2] */ 285 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 286 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 287 288 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 289 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 290 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 291 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 292 CONFIG_SYS_INIT_RAM_SIZE - \ 293 GENERATED_GBL_DATA_SIZE) 294 295 /* Defines for SPL */ 296 #define CONFIG_SPL_FRAMEWORK 297 #define CONFIG_SPL_BOARD_INIT 298 #define CONFIG_SPL_NAND_SIMPLE 299 300 #define CONFIG_SPL_NAND_BASE 301 #define CONFIG_SPL_NAND_DRIVERS 302 #define CONFIG_SPL_NAND_ECC 303 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 304 305 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 306 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 307 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 308 309 /* move malloc and bss high to prevent clashing with the main image */ 310 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 311 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 312 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 313 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 314 315 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 316 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 317 318 /* NAND boot config */ 319 #define CONFIG_SYS_NAND_PAGE_COUNT 64 320 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 321 #define CONFIG_SYS_NAND_OOBSIZE 64 322 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 323 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 324 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 325 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 326 48, 49, 50, 51, 52, 53, 54, 55,\ 327 56, 57, 58, 59, 60, 61, 62, 63} 328 #define CONFIG_SYS_NAND_ECCSIZE 256 329 #define CONFIG_SYS_NAND_ECCBYTES 3 330 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 331 #define CONFIG_SPL_NAND_SOFTECC 332 333 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 334 335 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 336 337 /* 338 * ethernet support 339 * 340 */ 341 #if defined(CONFIG_CMD_NET) 342 #define CONFIG_DRIVER_TI_EMAC 343 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 344 #define CONFIG_MII 345 #define CONFIG_BOOTP_DNS 346 #define CONFIG_BOOTP_DNS2 347 #define CONFIG_BOOTP_SEND_HOSTNAME 348 #define CONFIG_NET_RETRY_COUNT 10 349 #endif 350 351 #define CONFIG_SPLASH_SCREEN 352 #define CONFIG_VIDEO_BMP_RLE8 353 #define CONFIG_VIDEO_OMAP3 354 355 #endif /* __CONFIG_H */ 356