1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on omap3_evm_config.h 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_OMAP /* in a TI OMAP core */ 16 #define CONFIG_OMAP3_MCX /* working with mcx */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define MACH_TYPE_MCX 3656 25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 26 #define CONFIG_BOARD_LATE_INIT 27 28 29 #define CONFIG_SYS_CACHELINE_SIZE 64 30 31 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 32 33 #include <asm/arch/cpu.h> /* get chip and board defs */ 34 #include <asm/arch/omap.h> 35 36 /* 37 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 38 * and older u-boot.bin with the new U-Boot SPL. 39 */ 40 #define CONFIG_SYS_TEXT_BASE 0x80008000 41 42 /* 43 * Display CPU and Board information 44 */ 45 #define CONFIG_DISPLAY_CPUINFO 46 #define CONFIG_DISPLAY_BOARDINFO 47 48 /* Clock Defines */ 49 #define V_OSCK 26000000 /* Clock output from T2 */ 50 #define V_SCLK (V_OSCK >> 1) 51 52 #define CONFIG_MISC_INIT_R 53 54 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 55 #define CONFIG_SETUP_MEMORY_TAGS 56 #define CONFIG_INITRD_TAG 57 #define CONFIG_REVISION_TAG 58 59 /* 60 * Size of malloc() pool 61 */ 62 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 63 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 64 /* 65 * DDR related 66 */ 67 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 68 69 /* 70 * Hardware drivers 71 */ 72 73 /* 74 * NS16550 Configuration 75 */ 76 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 77 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 81 82 /* 83 * select serial console configuration 84 */ 85 #define CONFIG_CONS_INDEX 3 86 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 87 #define CONFIG_SERIAL3 3 /* UART3 */ 88 89 /* allow to overwrite serial and ethaddr */ 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_BAUDRATE 115200 92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93 115200} 94 #define CONFIG_MMC 95 #define CONFIG_OMAP_HSMMC 96 #define CONFIG_GENERIC_MMC 97 #define CONFIG_DOS_PARTITION 98 99 /* EHCI */ 100 #define CONFIG_USB_STORAGE 101 #define CONFIG_OMAP3_GPIO_2 102 #define CONFIG_OMAP3_GPIO_5 103 #define CONFIG_USB_EHCI 104 #define CONFIG_USB_EHCI_OMAP 105 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 106 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 107 #define CONFIG_USB_HOST_ETHER 108 #define CONFIG_USB_ETHER_ASIX 109 #define CONFIG_USB_ETHER_MCS7830 110 111 /* commands to include */ 112 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 113 #define CONFIG_CMD_FAT /* FAT support */ 114 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 115 116 #define CONFIG_CMD_DATE 117 #define CONFIG_CMD_MMC /* MMC support */ 118 #define CONFIG_CMD_FAT /* FAT support */ 119 #define CONFIG_CMD_NAND /* NAND support */ 120 #define CONFIG_CMD_CACHE 121 #define CONFIG_CMD_UBI 122 #define CONFIG_CMD_UBIFS 123 #define CONFIG_RBTREE 124 #define CONFIG_LZO 125 #define CONFIG_MTD_PARTITIONS 126 #define CONFIG_MTD_DEVICE 127 #define CONFIG_CMD_MTDPARTS 128 129 #define CONFIG_SYS_NO_FLASH 130 #define CONFIG_SYS_I2C 131 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 132 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 133 #define CONFIG_SYS_I2C_OMAP34XX 134 135 /* RTC */ 136 #define CONFIG_RTC_DS1337 137 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 138 139 #define CONFIG_CMD_MII 140 /* 141 * Board NAND Info. 142 */ 143 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 144 /* to access nand */ 145 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 146 /* to access */ 147 /* nand at CS0 */ 148 149 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 150 /* NAND devices */ 151 #define CONFIG_JFFS2_NAND 152 /* nand device jffs2 lives on */ 153 #define CONFIG_JFFS2_DEV "nand0" 154 /* start of jffs2 partition */ 155 #define CONFIG_JFFS2_PART_OFFSET 0x680000 156 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 157 158 /* Environment information */ 159 #define CONFIG_BOOTDELAY 3 160 161 #define CONFIG_BOOTFILE "uImage" 162 163 /* Setup MTD for NAND on the SOM */ 164 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 165 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 166 "1m(u-boot),256k(env1)," \ 167 "256k(env2),6m(kernel),6m(k_recovery)," \ 168 "8m(fs_recovery),-(common_data)" 169 170 #define CONFIG_HOSTNAME mcx 171 #define CONFIG_EXTRA_ENV_SETTINGS \ 172 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 173 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 174 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 175 "addfb=setenv bootargs ${bootargs} vram=6M " \ 176 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 177 "addip_sta=setenv bootargs ${bootargs} " \ 178 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 179 "${netmask}:${hostname}:eth0:off\0" \ 180 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 181 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 182 "else run addip_sta;fi\0" \ 183 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 184 "addtty=setenv bootargs ${bootargs} " \ 185 "console=${consoledev},${baudrate}\0" \ 186 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 187 "baudrate=115200\0" \ 188 "consoledev=ttyO2\0" \ 189 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 190 "loadaddr=0x82000000\0" \ 191 "load=tftp ${loadaddr} ${u-boot}\0" \ 192 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 193 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 194 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 195 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 196 "mmcargs=root=/dev/mmcblk0p2 rw " \ 197 "rootfstype=ext3 rootwait\0" \ 198 "mmcboot=echo Booting from mmc ...; " \ 199 "run mmcargs; " \ 200 "run addip addtty addmtd addfb addeth addmisc;" \ 201 "run loaduimage; " \ 202 "bootm ${loadaddr}\0" \ 203 "net_nfs=run load_k; " \ 204 "run nfsargs; " \ 205 "run addip addtty addmtd addfb addeth addmisc;" \ 206 "bootm ${loadaddr}\0" \ 207 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 208 "nfsroot=${serverip}:${rootpath}\0" \ 209 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 210 "uboot_addr=0x80000\0" \ 211 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 212 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 213 "updatemlo=nandecc hw;nand erase 0 20000;" \ 214 "nand write ${loadaddr} 0 20000\0" \ 215 "upd=if run load;then echo Updating u-boot;if run update;" \ 216 "then echo U-Boot updated;" \ 217 "else echo Error updating u-boot !;" \ 218 "echo Board without bootloader !!;" \ 219 "fi;" \ 220 "else echo U-Boot not downloaded..exiting;fi\0" \ 221 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 222 "bootscript=echo Running bootscript from mmc ...; " \ 223 "source ${loadaddr}\0" \ 224 "nandargs=setenv bootargs ubi.mtd=7 " \ 225 "root=ubi0:rootfs rootfstype=ubifs\0" \ 226 "nandboot=echo Booting from nand ...; " \ 227 "run nandargs; " \ 228 "ubi part nand0,4;" \ 229 "ubi readvol ${loadaddr} kernel;" \ 230 "run addtty addmtd addfb addeth addmisc;" \ 231 "bootm ${loadaddr}\0" \ 232 "preboot=ubi part nand0,7;" \ 233 "ubi readvol ${loadaddr} splash;" \ 234 "bmp display ${loadaddr};" \ 235 "gpio set 55\0" \ 236 "swupdate_args=setenv bootargs root=/dev/ram " \ 237 "quiet loglevel=1 " \ 238 "consoleblank=0 ${swupdate_misc}\0" \ 239 "swupdate=echo Running Sw-Update...;" \ 240 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 241 "else mtdparts default;fi; " \ 242 "ubi part nand0,5;" \ 243 "ubi readvol 0x82000000 kernel_recovery;" \ 244 "ubi part nand0,6;" \ 245 "ubi readvol 0x84000000 fs_recovery;" \ 246 "run swupdate_args; " \ 247 "setenv bootargs ${bootargs} " \ 248 "${mtdparts} " \ 249 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 250 "omapdss.def_disp=lcd;" \ 251 "bootm 0x82000000 0x84000000\0" \ 252 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 253 "then source 82000000;else run nandboot;fi\0" 254 255 #define CONFIG_AUTO_COMPLETE 256 #define CONFIG_CMDLINE_EDITING 257 258 /* 259 * Miscellaneous configurable options 260 */ 261 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 262 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 263 /* Print Buffer Size */ 264 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 265 sizeof(CONFIG_SYS_PROMPT) + 16) 266 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 267 /* args */ 268 /* Boot Argument Buffer Size */ 269 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 270 /* memtest works on */ 271 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 272 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 273 0x01F00000) /* 31MB */ 274 275 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 276 /* address */ 277 #define CONFIG_PREBOOT 278 279 /* 280 * AM3517 has 12 GP timers, they can be driven by the system clock 281 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 282 * This rate is divided by a local divisor. 283 */ 284 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 285 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 286 287 /* 288 * Physical Memory Map 289 */ 290 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 291 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 292 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 293 294 /* 295 * FLASH and environment organization 296 */ 297 298 /* **** PISMO SUPPORT *** */ 299 #define CONFIG_NAND 300 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 301 #define CONFIG_NAND_OMAP_GPMC 302 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 303 #define CONFIG_ENV_IS_IN_NAND 304 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 305 306 /* Redundant Environment */ 307 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 308 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 309 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 310 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 311 2 * CONFIG_SYS_ENV_SECT_SIZE) 312 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 313 314 /* Flash banks JFFS2 should use */ 315 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 316 CONFIG_SYS_MAX_NAND_DEVICE) 317 #define CONFIG_SYS_JFFS2_MEM_NAND 318 /* use flash_info[2] */ 319 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 320 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 321 322 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 323 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 324 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 325 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 326 CONFIG_SYS_INIT_RAM_SIZE - \ 327 GENERATED_GBL_DATA_SIZE) 328 329 /* Defines for SPL */ 330 #define CONFIG_SPL_FRAMEWORK 331 #define CONFIG_SPL_BOARD_INIT 332 #define CONFIG_SPL_NAND_SIMPLE 333 334 #define CONFIG_SPL_LIBCOMMON_SUPPORT 335 #define CONFIG_SPL_LIBDISK_SUPPORT 336 #define CONFIG_SPL_I2C_SUPPORT 337 #define CONFIG_SPL_MMC_SUPPORT 338 #define CONFIG_SPL_FAT_SUPPORT 339 #define CONFIG_SPL_LIBGENERIC_SUPPORT 340 #define CONFIG_SPL_SERIAL_SUPPORT 341 #define CONFIG_SPL_POWER_SUPPORT 342 #define CONFIG_SPL_NAND_SUPPORT 343 #define CONFIG_SPL_NAND_BASE 344 #define CONFIG_SPL_NAND_DRIVERS 345 #define CONFIG_SPL_NAND_ECC 346 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 347 348 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 349 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 350 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 351 352 /* move malloc and bss high to prevent clashing with the main image */ 353 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 354 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 355 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 356 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 357 358 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 359 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 360 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 361 362 /* NAND boot config */ 363 #define CONFIG_SYS_NAND_PAGE_COUNT 64 364 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 365 #define CONFIG_SYS_NAND_OOBSIZE 64 366 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 367 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 368 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 369 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 370 48, 49, 50, 51, 52, 53, 54, 55,\ 371 56, 57, 58, 59, 60, 61, 62, 63} 372 #define CONFIG_SYS_NAND_ECCSIZE 256 373 #define CONFIG_SYS_NAND_ECCBYTES 3 374 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 375 #define CONFIG_SPL_NAND_SOFTECC 376 377 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 378 379 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 380 381 /* 382 * ethernet support 383 * 384 */ 385 #if defined(CONFIG_CMD_NET) 386 #define CONFIG_DRIVER_TI_EMAC 387 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 388 #define CONFIG_MII 389 #define CONFIG_BOOTP_DNS 390 #define CONFIG_BOOTP_DNS2 391 #define CONFIG_BOOTP_SEND_HOSTNAME 392 #define CONFIG_NET_RETRY_COUNT 10 393 #endif 394 395 #define CONFIG_VIDEO 396 #define CONFIG_CFB_CONSOLE 397 #define CONFIG_VGA_AS_SINGLE_DEVICE 398 #define CONFIG_SPLASH_SCREEN 399 #define CONFIG_VIDEO_BMP_RLE8 400 #define CONFIG_CMD_BMP 401 #define CONFIG_VIDEO_OMAP3 402 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 403 404 #endif /* __CONFIG_H */ 405