1a4884831SStefan Roese /* 2a4884831SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3a4884831SStefan Roese * 4a4884831SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5a4884831SStefan Roese */ 6a4884831SStefan Roese 7a4884831SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8a4884831SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9a4884831SStefan Roese 10a4884831SStefan Roese /* 11a4884831SStefan Roese * High Level Configuration Options (easy to change) 12a4884831SStefan Roese */ 13a4884831SStefan Roese #define CONFIG_ARMADA_XP /* SOC Family Name */ 14a4884831SStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 15a4884831SStefan Roese #define CONFIG_SYS_GENERIC_BOARD 16a4884831SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 17a4884831SStefan Roese 18a4884831SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x04000000 19a4884831SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 20a4884831SStefan Roese 21a4884831SStefan Roese /* 22a4884831SStefan Roese * Commands configuration 23a4884831SStefan Roese */ 24a4884831SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 25a4884831SStefan Roese #include <config_cmd_default.h> 26a4884831SStefan Roese #define CONFIG_CMD_DHCP 27a4884831SStefan Roese #define CONFIG_CMD_ENV 28a4884831SStefan Roese #define CONFIG_CMD_I2C 29a4884831SStefan Roese #define CONFIG_CMD_PING 30a4884831SStefan Roese #define CONFIG_CMD_SF 31a4884831SStefan Roese #define CONFIG_CMD_SPI 32a4884831SStefan Roese #define CONFIG_CMD_TFTPPUT 33a4884831SStefan Roese #define CONFIG_CMD_TIME 34a4884831SStefan Roese 35a4884831SStefan Roese /* I2C */ 36a4884831SStefan Roese #define CONFIG_SYS_I2C 37a4884831SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 38a4884831SStefan Roese #define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE 39a4884831SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 40a4884831SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 41a4884831SStefan Roese 42a4884831SStefan Roese /* SPI NOR flash default params, used by sf commands */ 43a4884831SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 44a4884831SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 45a4884831SStefan Roese #define CONFIG_SPI_FLASH_STMICRO 46a4884831SStefan Roese 47a4884831SStefan Roese /* Environment in SPI NOR flash */ 48a4884831SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 49a4884831SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 50a4884831SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 51a4884831SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 52a4884831SStefan Roese 53a4884831SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 54a4884831SStefan Roese #define CONFIG_PHY_BASE_ADDR 0x0 55a4884831SStefan Roese #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 56a4884831SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 57a4884831SStefan Roese #define CONFIG_RESET_PHY_R 58a4884831SStefan Roese 59a4884831SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 60a4884831SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 61a4884831SStefan Roese 62a4884831SStefan Roese /* 63a4884831SStefan Roese * mv-common.h should be defined after CMD configs since it used them 64a4884831SStefan Roese * to enable certain macros 65a4884831SStefan Roese */ 66a4884831SStefan Roese #include "mv-common.h" 67a4884831SStefan Roese 68*e7778ec1SStefan Roese /* 69*e7778ec1SStefan Roese * Memory layout while starting into the bin_hdr via the 70*e7778ec1SStefan Roese * BootROM: 71*e7778ec1SStefan Roese * 72*e7778ec1SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 73*e7778ec1SStefan Roese * 0x4000.4030 bin_hdr start address 74*e7778ec1SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 75*e7778ec1SStefan Roese * 0x4007.fffc BootROM stack top 76*e7778ec1SStefan Roese * 77*e7778ec1SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 78*e7778ec1SStefan Roese * L2 cache thus cannot be used. 79*e7778ec1SStefan Roese */ 80*e7778ec1SStefan Roese 81*e7778ec1SStefan Roese /* SPL */ 82*e7778ec1SStefan Roese /* Defines for SPL */ 83*e7778ec1SStefan Roese #define CONFIG_SPL_FRAMEWORK 84*e7778ec1SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 85*e7778ec1SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 86*e7778ec1SStefan Roese 87*e7778ec1SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 88*e7778ec1SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 89*e7778ec1SStefan Roese 90*e7778ec1SStefan Roese #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 91*e7778ec1SStefan Roese CONFIG_SPL_BSS_MAX_SIZE) 92*e7778ec1SStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 93*e7778ec1SStefan Roese 94*e7778ec1SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 95*e7778ec1SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 96*e7778ec1SStefan Roese 97*e7778ec1SStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 98*e7778ec1SStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 99*e7778ec1SStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 100*e7778ec1SStefan Roese #define CONFIG_SPL_I2C_SUPPORT 101*e7778ec1SStefan Roese #define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" 102*e7778ec1SStefan Roese 103*e7778ec1SStefan Roese /* SPL related SPI defines */ 104*e7778ec1SStefan Roese #define CONFIG_SPL_SPI_SUPPORT 105*e7778ec1SStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 106*e7778ec1SStefan Roese #define CONFIG_SPL_SPI_LOAD 107*e7778ec1SStefan Roese #define CONFIG_SPL_SPI_BUS 0 108*e7778ec1SStefan Roese #define CONFIG_SPL_SPI_CS 0 109*e7778ec1SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 110*e7778ec1SStefan Roese 111*e7778ec1SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 112*e7778ec1SStefan Roese #define CONFIG_SYS_MVEBU_DDR 113*e7778ec1SStefan Roese #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 114*e7778ec1SStefan Roese 115a4884831SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 116