1a4884831SStefan Roese /* 2a4884831SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3a4884831SStefan Roese * 4a4884831SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5a4884831SStefan Roese */ 6a4884831SStefan Roese 7a4884831SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8a4884831SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9a4884831SStefan Roese 10a4884831SStefan Roese /* 11a4884831SStefan Roese * High Level Configuration Options (easy to change) 12a4884831SStefan Roese */ 13a4884831SStefan Roese #define CONFIG_ARMADA_XP /* SOC Family Name */ 14a4884831SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 15a4884831SStefan Roese 162923c2d2SStefan Roese /* 172923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 182923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 192923c2d2SStefan Roese * U-Boot into it. 202923c2d2SStefan Roese */ 212923c2d2SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 22a4884831SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 23a4884831SStefan Roese 24a4884831SStefan Roese /* 25a4884831SStefan Roese * Commands configuration 26a4884831SStefan Roese */ 27a4884831SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 28a4884831SStefan Roese #define CONFIG_CMD_DHCP 29a4884831SStefan Roese #define CONFIG_CMD_ENV 30a4884831SStefan Roese #define CONFIG_CMD_I2C 31a4884831SStefan Roese #define CONFIG_CMD_PING 32a4884831SStefan Roese #define CONFIG_CMD_SF 33a4884831SStefan Roese #define CONFIG_CMD_SPI 34a4884831SStefan Roese #define CONFIG_CMD_TFTPPUT 35a4884831SStefan Roese #define CONFIG_CMD_TIME 36a4884831SStefan Roese 37a4884831SStefan Roese /* I2C */ 38a4884831SStefan Roese #define CONFIG_SYS_I2C 39a4884831SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 40dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 41a4884831SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 42a4884831SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 43a4884831SStefan Roese 44a4884831SStefan Roese /* SPI NOR flash default params, used by sf commands */ 45a4884831SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 46a4884831SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 47a4884831SStefan Roese 48a4884831SStefan Roese /* Environment in SPI NOR flash */ 49a4884831SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 50a4884831SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 51a4884831SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 52a4884831SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 53a4884831SStefan Roese 54a4884831SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 55a4884831SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 56a4884831SStefan Roese 57a4884831SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 58a4884831SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 59a4884831SStefan Roese 60a4884831SStefan Roese /* 61a4884831SStefan Roese * mv-common.h should be defined after CMD configs since it used them 62a4884831SStefan Roese * to enable certain macros 63a4884831SStefan Roese */ 64a4884831SStefan Roese #include "mv-common.h" 65a4884831SStefan Roese 66e7778ec1SStefan Roese /* 67e7778ec1SStefan Roese * Memory layout while starting into the bin_hdr via the 68e7778ec1SStefan Roese * BootROM: 69e7778ec1SStefan Roese * 70e7778ec1SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 71e7778ec1SStefan Roese * 0x4000.4030 bin_hdr start address 72e7778ec1SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 73e7778ec1SStefan Roese * 0x4007.fffc BootROM stack top 74e7778ec1SStefan Roese * 75e7778ec1SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 76e7778ec1SStefan Roese * L2 cache thus cannot be used. 77e7778ec1SStefan Roese */ 78e7778ec1SStefan Roese 79e7778ec1SStefan Roese /* SPL */ 80e7778ec1SStefan Roese /* Defines for SPL */ 81e7778ec1SStefan Roese #define CONFIG_SPL_FRAMEWORK 82e7778ec1SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 83e7778ec1SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 84e7778ec1SStefan Roese 85e7778ec1SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 86e7778ec1SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 87e7778ec1SStefan Roese 886451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 896451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 906451223aSStefan Roese #endif 91e7778ec1SStefan Roese 92e7778ec1SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 93e7778ec1SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 94e7778ec1SStefan Roese 95e7778ec1SStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 96e7778ec1SStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 97e7778ec1SStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 98e7778ec1SStefan Roese #define CONFIG_SPL_I2C_SUPPORT 99e7778ec1SStefan Roese 100e7778ec1SStefan Roese /* SPL related SPI defines */ 101e7778ec1SStefan Roese #define CONFIG_SPL_SPI_SUPPORT 102e7778ec1SStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 103e7778ec1SStefan Roese #define CONFIG_SPL_SPI_LOAD 104e7778ec1SStefan Roese #define CONFIG_SPL_SPI_BUS 0 105e7778ec1SStefan Roese #define CONFIG_SPL_SPI_CS 0 106e7778ec1SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 107e7778ec1SStefan Roese 108e7778ec1SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 109ff9112dfSStefan Roese #define CONFIG_SYS_MVEBU_DDR_AXP 110e7778ec1SStefan Roese #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 111*698ffab2SStefan Roese #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 112e7778ec1SStefan Roese 113a4884831SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 114