1a4884831SStefan Roese /* 2a4884831SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3a4884831SStefan Roese * 4a4884831SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5a4884831SStefan Roese */ 6a4884831SStefan Roese 7a4884831SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8a4884831SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9a4884831SStefan Roese 10a4884831SStefan Roese /* 11a4884831SStefan Roese * High Level Configuration Options (easy to change) 12a4884831SStefan Roese */ 13a4884831SStefan Roese #define CONFIG_ARMADA_XP /* SOC Family Name */ 1442cc034fSStefan Roese #ifdef CONFIG_SPL_BUILD 15a4884831SStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 1642cc034fSStefan Roese #endif 17a4884831SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 18a4884831SStefan Roese 192923c2d2SStefan Roese /* 202923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 212923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 222923c2d2SStefan Roese * U-Boot into it. 232923c2d2SStefan Roese */ 242923c2d2SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 25a4884831SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 26a4884831SStefan Roese 27a4884831SStefan Roese /* 28a4884831SStefan Roese * Commands configuration 29a4884831SStefan Roese */ 30a4884831SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 31a4884831SStefan Roese #define CONFIG_CMD_DHCP 32a4884831SStefan Roese #define CONFIG_CMD_ENV 33a4884831SStefan Roese #define CONFIG_CMD_I2C 34a4884831SStefan Roese #define CONFIG_CMD_PING 35a4884831SStefan Roese #define CONFIG_CMD_SF 36a4884831SStefan Roese #define CONFIG_CMD_SPI 37a4884831SStefan Roese #define CONFIG_CMD_TFTPPUT 38a4884831SStefan Roese #define CONFIG_CMD_TIME 39a4884831SStefan Roese 40a4884831SStefan Roese /* I2C */ 41a4884831SStefan Roese #define CONFIG_SYS_I2C 42a4884831SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 43dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 44a4884831SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 45a4884831SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 46a4884831SStefan Roese 47a4884831SStefan Roese /* SPI NOR flash default params, used by sf commands */ 48a4884831SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 49a4884831SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 50a4884831SStefan Roese 51a4884831SStefan Roese /* Environment in SPI NOR flash */ 52a4884831SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 53a4884831SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 54a4884831SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 55a4884831SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 56a4884831SStefan Roese 57a4884831SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 58cae9008fSStefan Roese #define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 } 59a4884831SStefan Roese #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 60a4884831SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 61a4884831SStefan Roese #define CONFIG_RESET_PHY_R 62a4884831SStefan Roese 63a4884831SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 64a4884831SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 65a4884831SStefan Roese 66a4884831SStefan Roese /* 67a4884831SStefan Roese * mv-common.h should be defined after CMD configs since it used them 68a4884831SStefan Roese * to enable certain macros 69a4884831SStefan Roese */ 70a4884831SStefan Roese #include "mv-common.h" 71a4884831SStefan Roese 72e7778ec1SStefan Roese /* 73e7778ec1SStefan Roese * Memory layout while starting into the bin_hdr via the 74e7778ec1SStefan Roese * BootROM: 75e7778ec1SStefan Roese * 76e7778ec1SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 77e7778ec1SStefan Roese * 0x4000.4030 bin_hdr start address 78e7778ec1SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 79e7778ec1SStefan Roese * 0x4007.fffc BootROM stack top 80e7778ec1SStefan Roese * 81e7778ec1SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 82e7778ec1SStefan Roese * L2 cache thus cannot be used. 83e7778ec1SStefan Roese */ 84e7778ec1SStefan Roese 85e7778ec1SStefan Roese /* SPL */ 86e7778ec1SStefan Roese /* Defines for SPL */ 87e7778ec1SStefan Roese #define CONFIG_SPL_FRAMEWORK 88e7778ec1SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 89e7778ec1SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 90e7778ec1SStefan Roese 91e7778ec1SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 92e7778ec1SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 93e7778ec1SStefan Roese 94*6451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 95*6451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 96*6451223aSStefan Roese #endif 97e7778ec1SStefan Roese 98e7778ec1SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 99e7778ec1SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 100e7778ec1SStefan Roese 101e7778ec1SStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 102e7778ec1SStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 103e7778ec1SStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 104e7778ec1SStefan Roese #define CONFIG_SPL_I2C_SUPPORT 105e7778ec1SStefan Roese 106e7778ec1SStefan Roese /* SPL related SPI defines */ 107e7778ec1SStefan Roese #define CONFIG_SPL_SPI_SUPPORT 108e7778ec1SStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 109e7778ec1SStefan Roese #define CONFIG_SPL_SPI_LOAD 110e7778ec1SStefan Roese #define CONFIG_SPL_SPI_BUS 0 111e7778ec1SStefan Roese #define CONFIG_SPL_SPI_CS 0 112e7778ec1SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 113e7778ec1SStefan Roese 114e7778ec1SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 115ff9112dfSStefan Roese #define CONFIG_SYS_MVEBU_DDR_AXP 116e7778ec1SStefan Roese #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 117e7778ec1SStefan Roese 118a4884831SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 119