1a4884831SStefan Roese /* 2a4884831SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3a4884831SStefan Roese * 4a4884831SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5a4884831SStefan Roese */ 6a4884831SStefan Roese 7a4884831SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8a4884831SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9a4884831SStefan Roese 10a4884831SStefan Roese /* 11a4884831SStefan Roese * High Level Configuration Options (easy to change) 12a4884831SStefan Roese */ 13a4884831SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 14a4884831SStefan Roese 152923c2d2SStefan Roese /* 162923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 172923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 182923c2d2SStefan Roese * U-Boot into it. 192923c2d2SStefan Roese */ 202923c2d2SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 21a4884831SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22a4884831SStefan Roese 23a4884831SStefan Roese /* 24a4884831SStefan Roese * Commands configuration 25a4884831SStefan Roese */ 26a4884831SStefan Roese 27a4884831SStefan Roese /* I2C */ 28a4884831SStefan Roese #define CONFIG_SYS_I2C 29a4884831SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 30dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 31a4884831SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 32a4884831SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 33a4884831SStefan Roese 34a4884831SStefan Roese /* SPI NOR flash default params, used by sf commands */ 35a4884831SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 36a4884831SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 37a4884831SStefan Roese 38a4884831SStefan Roese /* Environment in SPI NOR flash */ 39a4884831SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 40a4884831SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 41a4884831SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 42a4884831SStefan Roese 43a4884831SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 44a4884831SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 45a4884831SStefan Roese 46a4884831SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 47a4884831SStefan Roese 48a4884831SStefan Roese /* 49a4884831SStefan Roese * mv-common.h should be defined after CMD configs since it used them 50a4884831SStefan Roese * to enable certain macros 51a4884831SStefan Roese */ 52a4884831SStefan Roese #include "mv-common.h" 53a4884831SStefan Roese 54e7778ec1SStefan Roese /* 55e7778ec1SStefan Roese * Memory layout while starting into the bin_hdr via the 56e7778ec1SStefan Roese * BootROM: 57e7778ec1SStefan Roese * 58e7778ec1SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 59e7778ec1SStefan Roese * 0x4000.4030 bin_hdr start address 60e7778ec1SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 61e7778ec1SStefan Roese * 0x4007.fffc BootROM stack top 62e7778ec1SStefan Roese * 63e7778ec1SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 64e7778ec1SStefan Roese * L2 cache thus cannot be used. 65e7778ec1SStefan Roese */ 66e7778ec1SStefan Roese 67e7778ec1SStefan Roese /* SPL */ 68e7778ec1SStefan Roese /* Defines for SPL */ 69e7778ec1SStefan Roese #define CONFIG_SPL_FRAMEWORK 70e7778ec1SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 71e7778ec1SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 72e7778ec1SStefan Roese 73e7778ec1SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 74e7778ec1SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 75e7778ec1SStefan Roese 766451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 776451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 786451223aSStefan Roese #endif 79e7778ec1SStefan Roese 80e7778ec1SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 81e7778ec1SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 82e7778ec1SStefan Roese 83e7778ec1SStefan Roese /* SPL related SPI defines */ 84e7778ec1SStefan Roese #define CONFIG_SPL_SPI_LOAD 85e7778ec1SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 86e7778ec1SStefan Roese 87e7778ec1SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 88e7778ec1SStefan Roese #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 89*698ffab2SStefan Roese #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 90e7778ec1SStefan Roese 91a4884831SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 92