1 /* 2 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 3 * on behalf of DENX Software Engineering GmbH 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 #ifndef __M28_H__ 21 #define __M28_H__ 22 23 #include <asm/arch/regs-base.h> 24 25 /* 26 * SoC configurations 27 */ 28 #define CONFIG_MX28 /* i.MX28 SoC */ 29 #define CONFIG_MXS_GPIO /* GPIO control */ 30 #define CONFIG_SYS_HZ 1000 /* Ticks per second */ 31 32 /* 33 * Define M28EVK machine type by hand until it lands in mach-types 34 */ 35 #define MACH_TYPE_M28EVK 3613 36 37 #define CONFIG_MACH_TYPE MACH_TYPE_M28EVK 38 39 #define CONFIG_SYS_NO_FLASH 40 #define CONFIG_SYS_ICACHE_OFF 41 #define CONFIG_SYS_DCACHE_OFF 42 #define CONFIG_BOARD_EARLY_INIT_F 43 #define CONFIG_ARCH_CPU_INIT 44 #define CONFIG_ARCH_MISC_INIT 45 46 /* 47 * SPL 48 */ 49 #define CONFIG_SPL 50 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE 51 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28" 52 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" 53 #define CONFIG_SPL_LIBCOMMON_SUPPORT 54 #define CONFIG_SPL_LIBGENERIC_SUPPORT 55 56 /* 57 * U-Boot Commands 58 */ 59 #include <config_cmd_default.h> 60 #define CONFIG_DISPLAY_CPUINFO 61 #define CONFIG_DOS_PARTITION 62 63 #define CONFIG_CMD_CACHE 64 #define CONFIG_CMD_DATE 65 #define CONFIG_CMD_DHCP 66 #define CONFIG_CMD_EEPROM 67 #define CONFIG_CMD_EXT2 68 #define CONFIG_CMD_FAT 69 #define CONFIG_CMD_GPIO 70 #define CONFIG_CMD_I2C 71 #define CONFIG_CMD_MII 72 #define CONFIG_CMD_MMC 73 #define CONFIG_CMD_NAND 74 #define CONFIG_CMD_NET 75 #define CONFIG_CMD_NFS 76 #define CONFIG_CMD_PING 77 #define CONFIG_CMD_SETEXPR 78 #define CONFIG_CMD_SF 79 #define CONFIG_CMD_SPI 80 #define CONFIG_CMD_USB 81 82 /* 83 * Memory configurations 84 */ 85 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ 86 #define PHYS_SDRAM_1 0x40000000 /* Base address */ 87 #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ 88 #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ 89 #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ 90 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ 91 #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ 92 #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ 93 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 94 /* Point initial SP in SRAM so SPL can use it too. */ 95 #define CONFIG_SYS_INIT_SP_ADDR 0x00002000 96 /* 97 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some 98 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot 99 * binary. In case there was more of this mess, 0x100 bytes are skipped. 100 */ 101 #define CONFIG_SYS_TEXT_BASE 0x40000100 102 103 /* 104 * U-Boot general configurations 105 */ 106 #define CONFIG_SYS_LONGHELP 107 #define CONFIG_SYS_PROMPT "=> " 108 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 109 #define CONFIG_SYS_PBSIZE \ 110 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 111 /* Print buffer size */ 112 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 113 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 114 /* Boot argument buffer size */ 115 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 116 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 117 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 118 #define CONFIG_SYS_HUSH_PARSER 119 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 120 121 /* 122 * Serial Driver 123 */ 124 #define CONFIG_PL011_SERIAL 125 #define CONFIG_PL011_CLOCK 24000000 126 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } 127 #define CONFIG_CONS_INDEX 0 128 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 129 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 130 131 /* 132 * MMC Driver 133 */ 134 #ifdef CONFIG_CMD_MMC 135 #define CONFIG_MMC 136 #define CONFIG_GENERIC_MMC 137 #define CONFIG_MXS_MMC 138 #endif 139 140 /* 141 * NAND 142 */ 143 #ifdef CONFIG_CMD_NAND 144 #define CONFIG_NAND_MXS 145 #define CONFIG_APBH_DMA 146 #define CONFIG_SYS_MAX_NAND_DEVICE 1 147 #define CONFIG_SYS_NAND_BASE 0x60000000 148 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 149 #define NAND_MAX_CHIPS 8 150 151 /* Environment is in NAND */ 152 #define CONFIG_ENV_IS_IN_NAND 153 #define CONFIG_ENV_SIZE (16 * 1024) 154 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 155 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 156 #define CONFIG_ENV_RANGE (512 * 1024) 157 #define CONFIG_ENV_OFFSET 0x300000 158 #define CONFIG_ENV_OFFSET_REDUND \ 159 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 160 161 #define CONFIG_CMD_UBI 162 #define CONFIG_CMD_UBIFS 163 #define CONFIG_CMD_MTDPARTS 164 #define CONFIG_RBTREE 165 #define CONFIG_LZO 166 #define CONFIG_MTD_DEVICE 167 #define CONFIG_MTD_PARTITIONS 168 #define MTDIDS_DEFAULT "nand0=gpmi-nand.0" 169 #define MTDPARTS_DEFAULT \ 170 "mtdparts=gpmi-nand.0:" \ 171 "3m(bootloader)ro," \ 172 "512k(environment)," \ 173 "512k(redundant-environment)," \ 174 "4m(kernel)," \ 175 "-(filesystem)" 176 #endif 177 178 /* 179 * Ethernet on SOC (FEC) 180 */ 181 #ifdef CONFIG_CMD_NET 182 #define CONFIG_NET_MULTI 183 #define CONFIG_ETHPRIME "FEC0" 184 #define CONFIG_FEC_MXC 185 #define CONFIG_FEC_MXC_MULTI 186 #define CONFIG_MII 187 #define CONFIG_DISCOVER_PHY 188 #define CONFIG_FEC_XCV_TYPE RMII 189 #endif 190 191 /* 192 * I2C 193 */ 194 #ifdef CONFIG_CMD_I2C 195 #define CONFIG_I2C_MXS 196 #define CONFIG_HARD_I2C 197 #define CONFIG_SYS_I2C_SPEED 400000 198 #endif 199 200 /* 201 * EEPROM 202 */ 203 #ifdef CONFIG_CMD_EEPROM 204 #define CONFIG_SYS_I2C_MULTI_EEPROMS 205 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 206 #endif 207 208 /* 209 * RTC 210 */ 211 #ifdef CONFIG_CMD_DATE 212 /* Use the internal RTC in the MXS chip */ 213 #define CONFIG_RTC_INTERNAL 214 #ifdef CONFIG_RTC_INTERNAL 215 #define CONFIG_RTC_MXS 216 #else 217 #define CONFIG_RTC_M41T62 218 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 219 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 220 #endif 221 #endif 222 223 /* 224 * USB 225 */ 226 #ifdef CONFIG_CMD_USB 227 #define CONFIG_USB_EHCI 228 #define CONFIG_USB_EHCI_MXS 229 #define CONFIG_EHCI_MXS_PORT 1 230 #define CONFIG_EHCI_IS_TDI 231 #define CONFIG_USB_STORAGE 232 #endif 233 234 /* 235 * SPI 236 */ 237 #ifdef CONFIG_CMD_SPI 238 #define CONFIG_HARD_SPI 239 #define CONFIG_MXS_SPI 240 #define CONFIG_SPI_HALF_DUPLEX 241 #define CONFIG_DEFAULT_SPI_BUS 2 242 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 243 244 /* SPI FLASH */ 245 #ifdef CONFIG_CMD_SF 246 #define CONFIG_SPI_FLASH 247 #define CONFIG_SPI_FLASH_STMICRO 248 #define CONFIG_SPI_FLASH_CS 2 249 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 250 #define CONFIG_SF_DEFAULT_SPEED 24000000 251 252 #define CONFIG_ENV_SPI_CS 0 253 #define CONFIG_ENV_SPI_BUS 2 254 #define CONFIG_ENV_SPI_MAX_HZ 24000000 255 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 256 #endif 257 #endif 258 259 /* 260 * Boot Linux 261 */ 262 #define CONFIG_CMDLINE_TAG 263 #define CONFIG_SETUP_MEMORY_TAGS 264 #define CONFIG_BOOTDELAY 3 265 #define CONFIG_BOOTFILE "uImage" 266 #define CONFIG_BOOTARGS "console=ttyAM0,115200n8 " 267 #define CONFIG_BOOTCOMMAND "run bootcmd_net" 268 #define CONFIG_LOADADDR 0x42000000 269 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 270 271 /* 272 * Extra Environments 273 */ 274 #define CONFIG_EXTRA_ENV_SETTINGS \ 275 "update_nand_full_filename=u-boot.nand\0" \ 276 "update_nand_firmware_filename=u-boot.sb\0" \ 277 "update_nand_firmware_maxsz=0x100000\0" \ 278 "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ 279 "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ 280 "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ 281 "nand device 0 ; " \ 282 "nand info ; " \ 283 "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ 284 "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ 285 "update_nand_full=" /* Update FCB, DBBT and FW */ \ 286 "if tftp ${update_nand_full_filename} ; then " \ 287 "run update_nand_get_fcb_size ; " \ 288 "nand scrub -y 0x0 ${filesize} ; " \ 289 "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \ 290 "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ 291 "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ 292 "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ 293 "fi\0" \ 294 "update_nand_firmware=" /* Update only firmware */ \ 295 "if tftp ${update_nand_firmware_filename} ; then " \ 296 "run update_nand_get_fcb_size ; " \ 297 "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ 298 "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ 299 "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ 300 "nand erase ${fcb_sz} ${fw_sz} ; " \ 301 "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ 302 "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ 303 "fi\0" 304 305 #endif /* __M28_H__ */ 306