1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_QDS_H 8 #define __LS2_QDS_H 9 10 #include "ls2080a_common.h" 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #define CONFIG_SYS_FSL_CLK 18 19 #ifdef CONFIG_FSL_QSPI 20 #define CONFIG_SYS_NO_FLASH 21 #undef CONFIG_CMD_IMLS 22 #define CONFIG_QIXIS_I2C_ACCESS 23 #define CONFIG_SYS_I2C_EARLY_INIT 24 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e 25 #endif 26 27 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 29 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 30 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 31 32 #define CONFIG_DDR_SPD 33 #define CONFIG_DDR_ECC 34 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 35 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 36 #define SPD_EEPROM_ADDRESS1 0x51 37 #define SPD_EEPROM_ADDRESS2 0x52 38 #define SPD_EEPROM_ADDRESS3 0x53 39 #define SPD_EEPROM_ADDRESS4 0x54 40 #define SPD_EEPROM_ADDRESS5 0x55 41 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ 42 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 43 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ 44 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 45 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 46 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 47 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 48 #endif 49 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 50 51 /* SATA */ 52 #define CONFIG_LIBATA 53 #define CONFIG_SCSI_AHCI 54 #define CONFIG_SCSI_AHCI_PLAT 55 #define CONFIG_SCSI 56 #define CONFIG_DOS_PARTITION 57 #define CONFIG_BOARD_LATE_INIT 58 59 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 60 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 61 62 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 63 #define CONFIG_SYS_SCSI_MAX_LUN 1 64 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 65 CONFIG_SYS_SCSI_MAX_LUN) 66 #define CONFIG_PARTITION_UUIDS 67 #define CONFIG_EFI_PARTITION 68 #define CONFIG_CMD_GPT 69 70 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ 71 72 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 73 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 74 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 75 76 #define CONFIG_SYS_NOR0_CSPR \ 77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 78 CSPR_PORT_SIZE_16 | \ 79 CSPR_MSEL_NOR | \ 80 CSPR_V) 81 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 83 CSPR_PORT_SIZE_16 | \ 84 CSPR_MSEL_NOR | \ 85 CSPR_V) 86 #define CONFIG_SYS_NOR1_CSPR \ 87 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 88 CSPR_PORT_SIZE_16 | \ 89 CSPR_MSEL_NOR | \ 90 CSPR_V) 91 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 92 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 93 CSPR_PORT_SIZE_16 | \ 94 CSPR_MSEL_NOR | \ 95 CSPR_V) 96 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 97 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 98 FTIM0_NOR_TEADC(0x5) | \ 99 FTIM0_NOR_TEAHC(0x5)) 100 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 101 FTIM1_NOR_TRAD_NOR(0x1a) |\ 102 FTIM1_NOR_TSEQRAD_NOR(0x13)) 103 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 104 FTIM2_NOR_TCH(0x4) | \ 105 FTIM2_NOR_TWPH(0x0E) | \ 106 FTIM2_NOR_TWP(0x1c)) 107 #define CONFIG_SYS_NOR_FTIM3 0x04000000 108 #define CONFIG_SYS_IFC_CCR 0x01000000 109 110 #ifndef CONFIG_SYS_NO_FLASH 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 114 #define CONFIG_SYS_FLASH_QUIET_TEST 115 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 116 117 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 121 122 #define CONFIG_SYS_FLASH_EMPTY_INFO 123 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 124 CONFIG_SYS_FLASH_BASE + 0x40000000} 125 #endif 126 127 #define CONFIG_NAND_FSL_IFC 128 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 129 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 130 131 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 132 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 133 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 134 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 135 | CSPR_V) 136 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 137 138 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 139 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 140 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 141 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 142 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 143 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 144 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 145 146 #define CONFIG_SYS_NAND_ONFI_DETECTION 147 148 /* ONFI NAND Flash mode0 Timing Params */ 149 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 150 FTIM0_NAND_TWP(0x18) | \ 151 FTIM0_NAND_TWCHT(0x07) | \ 152 FTIM0_NAND_TWH(0x0a)) 153 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 154 FTIM1_NAND_TWBE(0x39) | \ 155 FTIM1_NAND_TRR(0x0e) | \ 156 FTIM1_NAND_TRP(0x18)) 157 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 158 FTIM2_NAND_TREH(0x0a) | \ 159 FTIM2_NAND_TWHRE(0x1e)) 160 #define CONFIG_SYS_NAND_FTIM3 0x0 161 162 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 164 #define CONFIG_MTD_NAND_VERIFY_WRITE 165 #define CONFIG_CMD_NAND 166 167 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 168 169 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 170 #define QIXIS_LBMAP_SWITCH 0x06 171 #define QIXIS_LBMAP_MASK 0x0f 172 #define QIXIS_LBMAP_SHIFT 0 173 #define QIXIS_LBMAP_DFLTBANK 0x00 174 #define QIXIS_LBMAP_ALTBANK 0x04 175 #define QIXIS_LBMAP_NAND 0x09 176 #define QIXIS_LBMAP_QSPI 0x0f 177 #define QIXIS_RST_CTL_RESET 0x31 178 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 179 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 180 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 181 #define QIXIS_RCW_SRC_NAND 0x107 182 #define QIXIS_RCW_SRC_QSPI 0x62 183 #define QIXIS_RST_FORCE_MEM 0x01 184 185 #define CONFIG_SYS_CSPR3_EXT (0x0) 186 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 187 | CSPR_PORT_SIZE_8 \ 188 | CSPR_MSEL_GPCM \ 189 | CSPR_V) 190 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 191 | CSPR_PORT_SIZE_8 \ 192 | CSPR_MSEL_GPCM \ 193 | CSPR_V) 194 195 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 196 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) 197 /* QIXIS Timing parameters for IFC CS3 */ 198 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 199 FTIM0_GPCM_TEADC(0x0e) | \ 200 FTIM0_GPCM_TEAHC(0x0e)) 201 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 202 FTIM1_GPCM_TRAD(0x3f)) 203 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 204 FTIM2_GPCM_TCH(0xf) | \ 205 FTIM2_GPCM_TWP(0x3E)) 206 #define CONFIG_SYS_CS3_FTIM3 0x0 207 208 #if defined(CONFIG_SPL) && defined(CONFIG_NAND) 209 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 210 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY 211 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR 212 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 213 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 214 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 215 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 216 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 217 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 218 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 219 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY 220 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR 221 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY 222 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK 223 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 224 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 225 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 226 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 227 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 228 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 229 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 230 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 231 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 232 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 233 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 234 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 235 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 236 237 #define CONFIG_ENV_IS_IN_NAND 238 #define CONFIG_ENV_OFFSET (896 * 1024) 239 #define CONFIG_ENV_SECT_SIZE 0x20000 240 #define CONFIG_ENV_SIZE 0x2000 241 #define CONFIG_SPL_PAD_TO 0x20000 242 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) 243 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) 244 #else 245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 247 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 248 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 249 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 250 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 251 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 252 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 253 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 254 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 255 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 256 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 257 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 258 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 259 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 260 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 261 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 262 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 263 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 264 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 265 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 266 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 267 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 268 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 269 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 270 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 271 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 272 273 #if defined(CONFIG_QSPI_BOOT) 274 #define CONFIG_SYS_TEXT_BASE 0x20010000 275 #define CONFIG_ENV_IS_IN_SPI_FLASH 276 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 277 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 278 #define CONFIG_ENV_SECT_SIZE 0x10000 279 #else 280 #define CONFIG_ENV_IS_IN_FLASH 281 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 282 #define CONFIG_ENV_SECT_SIZE 0x20000 283 #define CONFIG_ENV_SIZE 0x2000 284 #endif 285 #endif 286 287 /* Debug Server firmware */ 288 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 289 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL 290 291 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 292 293 /* 294 * I2C 295 */ 296 #define I2C_MUX_PCA_ADDR 0x77 297 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 298 299 /* I2C bus multiplexer */ 300 #define I2C_MUX_CH_DEFAULT 0x8 301 302 /* SPI */ 303 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) 304 #define CONFIG_SPI_FLASH 305 306 #ifdef CONFIG_FSL_DSPI 307 #define CONFIG_SPI_FLASH_STMICRO 308 #define CONFIG_SPI_FLASH_SST 309 #define CONFIG_SPI_FLASH_EON 310 #endif 311 312 #ifdef CONFIG_FSL_QSPI 313 #define CONFIG_SPI_FLASH_SPANSION 314 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ 315 #define FSL_QSPI_FLASH_NUM 4 316 #endif 317 /* 318 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. 319 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 320 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 321 */ 322 #define FSL_QIXIS_BRDCFG9_QSPI 0x1 323 324 #endif 325 326 /* 327 * MMC 328 */ 329 #ifdef CONFIG_MMC 330 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 331 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 332 #endif 333 334 /* 335 * RTC configuration 336 */ 337 #define RTC 338 #define CONFIG_RTC_DS3231 1 339 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 340 #define CONFIG_CMD_DATE 341 342 /* EEPROM */ 343 #define CONFIG_ID_EEPROM 344 #define CONFIG_CMD_EEPROM 345 #define CONFIG_SYS_I2C_EEPROM_NXID 346 #define CONFIG_SYS_EEPROM_BUS_NUM 0 347 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 348 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 349 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 350 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 351 352 #define CONFIG_FSL_MEMAC 353 354 #ifdef CONFIG_PCI 355 #define CONFIG_PCI_SCAN_SHOW 356 #define CONFIG_CMD_PCI 357 #endif 358 359 /* MMC */ 360 #ifdef CONFIG_MMC 361 #define CONFIG_FSL_ESDHC 362 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 363 #define CONFIG_GENERIC_MMC 364 #define CONFIG_DOS_PARTITION 365 #endif 366 367 /* Initial environment variables */ 368 #undef CONFIG_EXTRA_ENV_SETTINGS 369 #define CONFIG_EXTRA_ENV_SETTINGS \ 370 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 371 "loadaddr=0x80100000\0" \ 372 "kernel_addr=0x100000\0" \ 373 "ramdisk_addr=0x800000\0" \ 374 "ramdisk_size=0x2000000\0" \ 375 "fdt_high=0xa0000000\0" \ 376 "initrd_high=0xffffffffffffffff\0" \ 377 "kernel_start=0x581100000\0" \ 378 "kernel_load=0xa0000000\0" \ 379 "kernel_size=0x2800000\0" \ 380 "mcinitcmd=fsl_mc start mc 0x580300000" \ 381 " 0x580800000 \0" 382 383 #ifdef CONFIG_FSL_MC_ENET 384 #define CONFIG_FSL_MEMAC 385 #define CONFIG_PHYLIB 386 #define CONFIG_PHYLIB_10G 387 #define CONFIG_PHY_VITESSE 388 #define CONFIG_PHY_REALTEK 389 #define CONFIG_PHY_TERANETICS 390 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 391 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 392 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 393 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 394 395 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 396 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 397 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 398 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 399 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 400 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 401 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 402 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 403 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 404 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 405 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 406 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 407 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 408 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 409 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 410 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 411 412 #define CONFIG_MII /* MII PHY management */ 413 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 414 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 415 416 #endif 417 418 /* 419 * USB 420 */ 421 #define CONFIG_HAS_FSL_XHCI_USB 422 #define CONFIG_USB_XHCI_FSL 423 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 424 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 425 426 #include <asm/fsl_secure_boot.h> 427 428 #endif /* __LS2_QDS_H */ 429