1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_MP 13 #define CONFIG_GICV3 14 #define CONFIG_FSL_TZPC_BP147 15 16 #include <asm/arch/ls2080a_stream_id.h> 17 #include <asm/arch/config.h> 18 19 /* Link Definitions */ 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 22 /* We need architecture specific misc initializations */ 23 #define CONFIG_ARCH_MISC_INIT 24 25 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 26 27 /* Link Definitions */ 28 #ifndef CONFIG_QSPI_BOOT 29 #ifdef CONFIG_SPL 30 #define CONFIG_SYS_TEXT_BASE 0x80400000 31 #else 32 #define CONFIG_SYS_TEXT_BASE 0x30100000 33 #endif 34 #endif 35 36 #ifdef CONFIG_EMU 37 #define CONFIG_SYS_NO_FLASH 38 #endif 39 40 #define CONFIG_SUPPORT_RAW_INITRD 41 42 #define CONFIG_SKIP_LOWLEVEL_INIT 43 44 #ifndef CONFIG_SPL 45 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 46 #endif 47 #ifndef CONFIG_SYS_FSL_DDR4 48 #define CONFIG_SYS_DDR_RAW_TIMING 49 #endif 50 51 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 52 53 #define CONFIG_VERY_BIG_RAM 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 55 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 58 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 59 60 /* 61 * SMP Definitinos 62 */ 63 #define CPU_RELEASE_ADDR secondary_boot_func 64 65 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 66 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 67 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 68 /* 69 * DDR controller use 0 as the base address for binding. 70 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 71 */ 72 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 73 #define CONFIG_DP_DDR_CTRL 2 74 #define CONFIG_DP_DDR_NUM_CTRLS 1 75 #endif 76 77 /* Generic Timer Definitions */ 78 /* 79 * This is not an accurate number. It is used in start.S. The frequency 80 * will be udpated later when get_bus_freq(0) is available. 81 */ 82 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 83 84 /* Size of malloc() pool */ 85 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 86 87 /* I2C */ 88 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_I2C_MXC 90 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 91 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 92 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 93 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 94 95 /* Serial Port */ 96 #define CONFIG_CONS_INDEX 1 97 #define CONFIG_SYS_NS16550_SERIAL 98 #define CONFIG_SYS_NS16550_REG_SIZE 1 99 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 100 101 #define CONFIG_BAUDRATE 115200 102 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 103 104 /* IFC */ 105 #define CONFIG_FSL_IFC 106 107 /* 108 * During booting, IFC is mapped at the region of 0x30000000. 109 * But this region is limited to 256MB. To accommodate NOR, promjet 110 * and FPGA. This region is divided as below: 111 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 112 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 113 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 114 * 115 * To accommodate bigger NOR flash and other devices, we will map IFC 116 * chip selects to as below: 117 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 118 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 119 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 120 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 121 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 122 * 123 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 124 * CONFIG_SYS_FLASH_BASE has the final address (core view) 125 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 126 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 127 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 128 */ 129 130 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 131 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 132 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 133 134 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 135 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 136 137 #ifndef __ASSEMBLY__ 138 unsigned long long get_qixis_addr(void); 139 #endif 140 #define QIXIS_BASE get_qixis_addr() 141 #define QIXIS_BASE_PHYS 0x20000000 142 #define QIXIS_BASE_PHYS_EARLY 0xC000000 143 #define QIXIS_STAT_PRES1 0xb 144 #define QIXIS_SDID_MASK 0x07 145 #define QIXIS_ESDHC_NO_ADAPTER 0x7 146 147 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 148 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 149 150 /* MC firmware */ 151 #define CONFIG_FSL_MC_ENET 152 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 153 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 154 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 155 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 156 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 157 /* For LS2085A */ 158 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 159 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 160 161 /* 162 * Carve out a DDR region which will not be used by u-boot/Linux 163 * 164 * It will be used by MC and Debug Server. The MC region must be 165 * 512MB aligned, so the min size to hide is 512MB. 166 */ 167 #ifdef CONFIG_FSL_MC_ENET 168 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 169 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) 170 #endif 171 172 /* Command line configuration */ 173 #define CONFIG_CMD_ENV 174 175 /* Miscellaneous configurable options */ 176 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 177 178 /* Physical Memory Map */ 179 /* fixme: these need to be checked against the board */ 180 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 181 182 #define CONFIG_NR_DRAM_BANKS 3 183 184 #define CONFIG_HWCONFIG 185 #define HWCONFIG_BUFFER_SIZE 128 186 187 /* Allow to overwrite serial and ethaddr */ 188 #define CONFIG_ENV_OVERWRITE 189 190 /* Initial environment variables */ 191 #define CONFIG_EXTRA_ENV_SETTINGS \ 192 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 193 "loadaddr=0x80100000\0" \ 194 "kernel_addr=0x100000\0" \ 195 "ramdisk_addr=0x800000\0" \ 196 "ramdisk_size=0x2000000\0" \ 197 "fdt_high=0xa0000000\0" \ 198 "initrd_high=0xffffffffffffffff\0" \ 199 "kernel_start=0x581200000\0" \ 200 "kernel_load=0xa0000000\0" \ 201 "kernel_size=0x2800000\0" \ 202 "console=ttyAMA0,38400n8\0" \ 203 "mcinitcmd=fsl_mc start mc 0x580300000" \ 204 " 0x580800000 \0" 205 206 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 207 "earlycon=uart8250,mmio,0x21c0500 " \ 208 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 209 " hugepagesz=2m hugepages=256" 210 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ 211 " cp.b $kernel_start $kernel_load" \ 212 " $kernel_size && bootm $kernel_load" 213 214 /* Monitor Command Prompt */ 215 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 216 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 217 sizeof(CONFIG_SYS_PROMPT) + 16) 218 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 219 #define CONFIG_SYS_LONGHELP 220 #define CONFIG_CMDLINE_EDITING 1 221 #define CONFIG_AUTO_COMPLETE 222 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 223 224 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 225 226 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 227 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 228 #define CONFIG_SPL_FRAMEWORK 229 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 230 #define CONFIG_SPL_MAX_SIZE 0x16000 231 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 232 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 233 #define CONFIG_SPL_TEXT_BASE 0x1800a000 234 235 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 236 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 237 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 238 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 239 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) 240 241 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 242 243 /* Hash command with SHA acceleration supported in hardware */ 244 #ifdef CONFIG_FSL_CAAM 245 #define CONFIG_CMD_HASH 246 #define CONFIG_SHA_HW_ACCEL 247 #endif 248 249 #endif /* __LS2_COMMON_H */ 250