1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x82000000 16 #elif defined(CONFIG_QSPI_BOOT) 17 #define CONFIG_SYS_TEXT_BASE 0x40010000 18 #else 19 #define CONFIG_SYS_TEXT_BASE 0x60100000 20 #endif 21 22 #ifndef __ASSEMBLY__ 23 unsigned long get_board_sys_clk(void); 24 unsigned long get_board_ddr_clk(void); 25 #endif 26 27 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 28 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 29 30 #define CONFIG_SKIP_LOWLEVEL_INIT 31 32 #define CONFIG_LAYERSCAPE_NS_ACCESS 33 34 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 35 /* Physical Memory Map */ 36 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 37 #define CONFIG_NR_DRAM_BANKS 2 38 39 #define CONFIG_DDR_SPD 40 #define SPD_EEPROM_ADDRESS 0x51 41 #define CONFIG_SYS_SPD_BUS_NUM 0 42 43 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 44 45 #define CONFIG_DDR_ECC 46 #ifdef CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 51 #define CONFIG_SYS_HAS_SERDES 52 53 /* DSPI */ 54 #ifdef CONFIG_FSL_DSPI 55 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 56 #define CONFIG_SPI_FLASH_SST /* cs1 */ 57 #define CONFIG_SPI_FLASH_EON /* cs2 */ 58 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 59 #define CONFIG_SF_DEFAULT_BUS 1 60 #define CONFIG_SF_DEFAULT_CS 0 61 #endif 62 #endif 63 64 /* QSPI */ 65 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 66 #ifdef CONFIG_FSL_QSPI 67 #define CONFIG_SPI_FLASH_SPANSION 68 #define FSL_QSPI_FLASH_SIZE (1 << 24) 69 #define FSL_QSPI_FLASH_NUM 2 70 #endif 71 #endif 72 73 #ifdef CONFIG_SYS_DPAA_FMAN 74 #define CONFIG_FMAN_ENET 75 #define CONFIG_PHYLIB 76 #define CONFIG_PHY_VITESSE 77 #define CONFIG_PHY_REALTEK 78 #define CONFIG_PHYLIB_10G 79 #define RGMII_PHY1_ADDR 0x1 80 #define RGMII_PHY2_ADDR 0x2 81 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 82 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 83 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 84 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 85 /* PHY address on QSGMII riser card on slot 2 */ 86 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 87 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 88 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 89 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 90 #endif 91 92 #ifdef CONFIG_RAMBOOT_PBL 93 #define CONFIG_SYS_FSL_PBL_PBI \ 94 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 95 #endif 96 97 #ifdef CONFIG_NAND_BOOT 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 100 #endif 101 102 #ifdef CONFIG_SD_BOOT 103 #ifdef CONFIG_SD_BOOT_QSPI 104 #define CONFIG_SYS_FSL_PBL_RCW \ 105 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 106 #else 107 #define CONFIG_SYS_FSL_PBL_RCW \ 108 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 109 #endif 110 #endif 111 112 /* IFC */ 113 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 114 #define CONFIG_FSL_IFC 115 /* 116 * CONFIG_SYS_FLASH_BASE has the final address (core view) 117 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 118 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 119 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 120 */ 121 #define CONFIG_SYS_FLASH_BASE 0x60000000 122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 123 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 124 125 #ifndef CONFIG_SYS_NO_FLASH 126 #define CONFIG_FLASH_CFI_DRIVER 127 #define CONFIG_SYS_FLASH_CFI 128 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 129 #define CONFIG_SYS_FLASH_QUIET_TEST 130 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 131 #endif 132 #endif 133 134 /* SATA */ 135 #define CONFIG_LIBATA 136 #define CONFIG_SCSI_AHCI 137 #define CONFIG_SCSI_AHCI_PLAT 138 #define CONFIG_SCSI 139 #define CONFIG_DOS_PARTITION 140 #define CONFIG_BOARD_LATE_INIT 141 142 /* EEPROM */ 143 #define CONFIG_ID_EEPROM 144 #define CONFIG_SYS_I2C_EEPROM_NXID 145 #define CONFIG_SYS_EEPROM_BUS_NUM 0 146 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 149 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 150 151 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 152 153 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 154 #define CONFIG_SYS_SCSI_MAX_LUN 1 155 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 156 CONFIG_SYS_SCSI_MAX_LUN) 157 158 /* 159 * IFC Definitions 160 */ 161 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 162 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 163 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 164 CSPR_PORT_SIZE_16 | \ 165 CSPR_MSEL_NOR | \ 166 CSPR_V) 167 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 168 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 169 + 0x8000000) | \ 170 CSPR_PORT_SIZE_16 | \ 171 CSPR_MSEL_NOR | \ 172 CSPR_V) 173 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 174 175 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 176 CSOR_NOR_TRHZ_80) 177 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 178 FTIM0_NOR_TEADC(0x5) | \ 179 FTIM0_NOR_TEAHC(0x5)) 180 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 181 FTIM1_NOR_TRAD_NOR(0x1a) | \ 182 FTIM1_NOR_TSEQRAD_NOR(0x13)) 183 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 184 FTIM2_NOR_TCH(0x4) | \ 185 FTIM2_NOR_TWPH(0xe) | \ 186 FTIM2_NOR_TWP(0x1c)) 187 #define CONFIG_SYS_NOR_FTIM3 0 188 189 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 196 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 197 198 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 199 #define CONFIG_SYS_WRITE_SWAPPED_DATA 200 201 /* 202 * NAND Flash Definitions 203 */ 204 #define CONFIG_NAND_FSL_IFC 205 206 #define CONFIG_SYS_NAND_BASE 0x7e800000 207 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 208 209 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 210 211 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 212 | CSPR_PORT_SIZE_8 \ 213 | CSPR_MSEL_NAND \ 214 | CSPR_V) 215 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 216 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 217 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 218 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 219 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 220 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 221 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 222 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 223 224 #define CONFIG_SYS_NAND_ONFI_DETECTION 225 226 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 227 FTIM0_NAND_TWP(0x18) | \ 228 FTIM0_NAND_TWCHT(0x7) | \ 229 FTIM0_NAND_TWH(0xa)) 230 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 231 FTIM1_NAND_TWBE(0x39) | \ 232 FTIM1_NAND_TRR(0xe) | \ 233 FTIM1_NAND_TRP(0x18)) 234 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 235 FTIM2_NAND_TREH(0xa) | \ 236 FTIM2_NAND_TWHRE(0x1e)) 237 #define CONFIG_SYS_NAND_FTIM3 0x0 238 239 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 240 #define CONFIG_SYS_MAX_NAND_DEVICE 1 241 #define CONFIG_MTD_NAND_VERIFY_WRITE 242 #define CONFIG_CMD_NAND 243 244 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 245 #endif 246 247 #ifdef CONFIG_NAND_BOOT 248 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 249 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 250 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 251 #endif 252 253 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 254 #define CONFIG_QIXIS_I2C_ACCESS 255 #define CONFIG_SYS_I2C_EARLY_INIT 256 #define CONFIG_SYS_NO_FLASH 257 #endif 258 259 /* 260 * QIXIS Definitions 261 */ 262 #define CONFIG_FSL_QIXIS 263 264 #ifdef CONFIG_FSL_QIXIS 265 #define QIXIS_BASE 0x7fb00000 266 #define QIXIS_BASE_PHYS QIXIS_BASE 267 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 268 #define QIXIS_LBMAP_SWITCH 6 269 #define QIXIS_LBMAP_MASK 0x0f 270 #define QIXIS_LBMAP_SHIFT 0 271 #define QIXIS_LBMAP_DFLTBANK 0x00 272 #define QIXIS_LBMAP_ALTBANK 0x04 273 #define QIXIS_LBMAP_NAND 0x09 274 #define QIXIS_LBMAP_SD 0x00 275 #define QIXIS_LBMAP_SD_QSPI 0xff 276 #define QIXIS_LBMAP_QSPI 0xff 277 #define QIXIS_RCW_SRC_NAND 0x110 278 #define QIXIS_RCW_SRC_SD 0x040 279 #define QIXIS_RCW_SRC_QSPI 0x045 280 #define QIXIS_RST_CTL_RESET 0x41 281 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 282 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 283 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 284 285 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 286 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 287 CSPR_PORT_SIZE_8 | \ 288 CSPR_MSEL_GPCM | \ 289 CSPR_V) 290 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 291 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 292 CSOR_NOR_NOR_MODE_AVD_NOR | \ 293 CSOR_NOR_TRHZ_80) 294 295 /* 296 * QIXIS Timing parameters for IFC GPCM 297 */ 298 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 299 FTIM0_GPCM_TEADC(0x20) | \ 300 FTIM0_GPCM_TEAHC(0x10)) 301 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 302 FTIM1_GPCM_TRAD(0x1f)) 303 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 304 FTIM2_GPCM_TCH(0x8) | \ 305 FTIM2_GPCM_TWP(0xf0)) 306 #define CONFIG_SYS_FPGA_FTIM3 0x0 307 #endif 308 309 #ifdef CONFIG_NAND_BOOT 310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 318 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 327 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 328 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 335 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 336 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 337 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 338 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 339 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 340 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 341 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 342 #else 343 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 352 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 353 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 360 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 361 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 362 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 363 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 364 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 365 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 366 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 367 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 368 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 369 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 370 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 371 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 372 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 373 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 374 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 375 #endif 376 377 /* 378 * I2C bus multiplexer 379 */ 380 #define I2C_MUX_PCA_ADDR_PRI 0x77 381 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 382 #define I2C_RETIMER_ADDR 0x18 383 #define I2C_MUX_CH_DEFAULT 0x8 384 #define I2C_MUX_CH_CH7301 0xC 385 #define I2C_MUX_CH5 0xD 386 #define I2C_MUX_CH6 0xE 387 #define I2C_MUX_CH7 0xF 388 389 #define I2C_MUX_CH_VOL_MONITOR 0xa 390 391 /* Voltage monitor on channel 2*/ 392 #define I2C_VOL_MONITOR_ADDR 0x40 393 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 394 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 395 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 396 397 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 398 #ifndef CONFIG_SPL_BUILD 399 #define CONFIG_VID 400 #endif 401 #define CONFIG_VOL_MONITOR_IR36021_SET 402 #define CONFIG_VOL_MONITOR_INA220 403 /* The lowest and highest voltage allowed for LS1046AQDS */ 404 #define VDD_MV_MIN 819 405 #define VDD_MV_MAX 1212 406 407 /* 408 * Miscellaneous configurable options 409 */ 410 #define CONFIG_MISC_INIT_R 411 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 412 #define CONFIG_AUTO_COMPLETE 413 #define CONFIG_SYS_PBSIZE \ 414 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 415 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 416 417 #define CONFIG_SYS_MEMTEST_START 0x80000000 418 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 419 420 #define CONFIG_SYS_HZ 1000 421 422 /* 423 * Stack sizes 424 * The stack sizes are set up in start.S using the settings below 425 */ 426 #define CONFIG_STACKSIZE (30 * 1024) 427 428 #define CONFIG_SYS_INIT_SP_OFFSET \ 429 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 430 431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 432 433 /* 434 * Environment 435 */ 436 #define CONFIG_ENV_OVERWRITE 437 438 #ifdef CONFIG_NAND_BOOT 439 #define CONFIG_ENV_IS_IN_NAND 440 #define CONFIG_ENV_SIZE 0x2000 441 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 442 #elif defined(CONFIG_SD_BOOT) 443 #define CONFIG_ENV_OFFSET (1024 * 1024) 444 #define CONFIG_ENV_IS_IN_MMC 445 #define CONFIG_SYS_MMC_ENV_DEV 0 446 #define CONFIG_ENV_SIZE 0x2000 447 #elif defined(CONFIG_QSPI_BOOT) 448 #define CONFIG_ENV_IS_IN_SPI_FLASH 449 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 450 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 451 #define CONFIG_ENV_SECT_SIZE 0x10000 452 #else 453 #define CONFIG_ENV_IS_IN_FLASH 454 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 455 #define CONFIG_ENV_SECT_SIZE 0x20000 456 #define CONFIG_ENV_SIZE 0x20000 457 #endif 458 459 #define CONFIG_CMDLINE_TAG 460 461 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 462 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 463 "e0000 f00000 && bootm $kernel_load" 464 #else 465 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 466 "$kernel_size && bootm $kernel_load" 467 #endif 468 469 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 470 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ 471 "14m(free)" 472 #else 473 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 474 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 475 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 476 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 477 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 478 "40m(nor_bank4_fit);7e800000.flash:" \ 479 "4m(nand_uboot),36m(nand_kernel)," \ 480 "472m(nand_free);spi0.0:2m(uboot)," \ 481 "14m(free)" 482 #endif 483 484 #include <asm/fsl_secure_boot.h> 485 486 #endif /* __LS1046AQDS_H__ */ 487